[Uboot-stm32] [PATCH] clk: stm32: Wrong macros used in register read

[Patrice CHOTARD]

On 7/28/25 10:47, Patrice CHOTARD wrote:
> 
> 
> On 7/24/25 13:37, Andrew Goodbody wrote:
>> Smatch reported a warning about a shift macro being used as a mask. Make
>> the obvious changes to make this register read calculation work the same
>> as the previous ones.
>>
>> Signed-off-by: Andrew Goodbody <andrew.goodbody at linaro.org>
>> ---
>> This fix is somewhat speculative as it is being made without
>> reference to any manual.
>> ---
>>  drivers/clk/stm32/clk-stm32h7.c | 4 ++--
>>  1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/clk/stm32/clk-stm32h7.c b/drivers/clk/stm32/clk-stm32h7.c
>> index aa3be414a29..df82db69738 100644
>> --- a/drivers/clk/stm32/clk-stm32h7.c
>> +++ b/drivers/clk/stm32/clk-stm32h7.c
>> @@ -549,8 +549,8 @@ static u32 stm32_get_PLL1_rate(struct stm32_rcc_regs *regs,
>>  	divr1 = readl(&regs->pll1divr) & RCC_PLL1DIVR_DIVR1_MASK;
>>  	divr1 = (divr1 >> RCC_PLL1DIVR_DIVR1_SHIFT) + 1;
>>  
>> -	fracn1 = readl(&regs->pll1fracr) & RCC_PLL1DIVR_DIVR1_MASK;
>> -	fracn1 = fracn1 & RCC_PLL1DIVR_DIVR1_SHIFT;
>> +	fracn1 = readl(&regs->pll1fracr) & RCC_PLL1FRACR_FRACN1_MASK;
>> +	fracn1 = (fracn1 >> RCC_PLL1FRACR_FRACN1_SHIFT) + 1;
>>  
>>  	vco = (pllsrc / divm1) * divn1;
>>  	rate = (pllsrc * fracn1) / (divm1 * 8192);
>>
>> ---
>> base-commit: 3532f1f5edfc97c9dcea723cdeb732eda44bc669
>> change-id: 20250724-clk_stm32-b097d32f3fe9
>>
>> Best regards,
> 
> Hi Andrew
> 
> Reviewed-by: Patrice Chotard <patrice.chotard at foss.st.com>
> 
> Thanks

Applied to u-boot-stm32/master

Thanks
Patrice

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