[PATCH 2/5] riscv: cpu: th1520: Support cache enabling/disabling in M mode only

[Leo Liang]

On Fri, May 30, 2025 at 09:48:48AM +0000, Yao Zi wrote:
> [EXTERNAL MAIL]
> 
> These operations rely on a customized M-mode CSR, MHCR, which isn't
> available when running in S mode.
> 
> Let's fallback to the generic weak stub when running in S mode to avoid
> illegal accesses.
> 
> Signed-off-by: Yao Zi <ziyao at disroot.org>
> ---
>  arch/riscv/cpu/th1520/cache.c | 2 ++
>  1 file changed, 2 insertions(+)

Reviewed-by: Leo Yu-Chi Liang <ycliang at andestech.com>