[PATCH v2 0/5] Introduce support for QCS615 SoC based Platform

[Casey Connolly]

On 5/21/25 05:53, Aswin Murugan wrote:
> These patches introduce the initial support code needed
> for the Qualcomm QCS615 SoC IQ6 based Platform.
> 
> Please see [1] for SoC related details

Thanks!

Reviewed-by: Casey Connolly <casey.connolly at linaro.org>

> 
> Thanks
> Aswin
> 
> 1 - https://docs.qualcomm.com/bundle/publicresource/87-83838-1_REV_A_Qualcomm_IQ6_Series_Product_Brief.pdf
> 
> Signed-off-by: Aswin Murugan <aswin.murugan at oss.qualcomm.com>
> ---
> Changes in v2:
> - Replaced the "1" with BIT(0) in drivers/clk/qcom/clock-qcs615.c
> - Link to v1: https://lore.kernel.org/u-boot/20250513110213.330495-1-aswin.murugan@oss.qualcomm.com/
> ---
> 
> Aswin Murugan (5):
>    dts: qcs615-ride-u-boot.dtsi: Add memory entry to bootup
>    phy: qcom: Enable QMP UFS PHY driver for QCS615
>    clk/qcom: qcs615: Add GCC clock driver for QCS615
>    qcom_defconfig: Enable QCS615 clock driver
>    configs: add qcs615_defconfig
> 
>   arch/arm/dts/qcs615-ride-u-boot.dtsi |  14 +++
>   configs/qcom_defconfig               |   1 +
>   configs/qcom_qcs615_defconfig        |  22 ++++
>   drivers/clk/qcom/Kconfig             |   8 ++
>   drivers/clk/qcom/Makefile            |   1 +
>   drivers/clk/qcom/clock-qcs615.c      | 163 +++++++++++++++++++++++++++
>   drivers/phy/qcom/phy-qcom-qmp-ufs.c  | 127 +++++++++++++++++++++
>   7 files changed, 336 insertions(+)
>   create mode 100644 arch/arm/dts/qcs615-ride-u-boot.dtsi
>   create mode 100644 configs/qcom_qcs615_defconfig
>   create mode 100644 drivers/clk/qcom/clock-qcs615.c
> 

-- 
Casey (she/they)