[PATCH v1] mach-k3: am62ax: enable caches for the SPL stage

[Tom Rini]

On Thu, May 22, 2025 at 06:03:04PM +0530, Anshul Dalal wrote:

> board_init_f for the am62a is missing the call to spl_enable_cache which
> exists for all other am62 platforms (check am625_init.c &
> am62p5_init.c).
> 
> This allows the usage of caches while loading and parsing the u-boot.img
> FIT resulting in ~2x speedup in the A53 SPL stage.
> 
> Signed-off-by: Anshul Dalal <anshuld at ti.com>
> ---
>  arch/arm/mach-k3/am62ax/am62a7_init.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm/mach-k3/am62ax/am62a7_init.c b/arch/arm/mach-k3/am62ax/am62a7_init.c
> index 52a21277227..1d8644bd073 100644
> --- a/arch/arm/mach-k3/am62ax/am62a7_init.c
> +++ b/arch/arm/mach-k3/am62ax/am62a7_init.c
> @@ -191,6 +191,7 @@ void board_init_f(ulong dummy)
>  	if (ret)
>  		panic("DRAM init failed: %d\n", ret);
>  #endif
> +	spl_enable_cache();
>  
>  	setup_qos();

This is, as it matches all of the other K3 platforms, almost, fine
enough. But can we consolidate board_init_f for K3 anywhere? It seems
like there's a whole of lot repetition in there between otherwise
similar code paths. And then there's the few platforms that call
spl_enable_caches in k3_mem_init instead, why? Thanks.

-- 
Tom
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