[PATCH v3 7/7] drivers: ddr: altera: Fix Cylcone5 SPL boot loop issue

[Ravulapalli, Naresh Kumar]

Hi Tien Fong

On 10-Jun-25 8:13 AM, Chee, Tien Fong wrote:
> Hi,
> 
>> -----Original Message-----
>> From: Ravulapalli, Naresh Kumar <naresh.kumar.ravulapalli at altera.com>
>> Sent: Tuesday, June 3, 2025 7:55 PM
>> To: u-boot at lists.denx.de
>> Cc: Marek Vasut <marex at denx.de>; Simon Goldschmidt
>> <simon.k.r.goldschmidt at gmail.com>; Chee, Tien Fong
>> <tien.fong.chee at altera.com>; Tom Rini <trini at konsulko.com>; Ravulapalli,
>> Naresh Kumar <naresh.kumar.ravulapalli at altera.com>; Romli, Khairul Anuar
>> <khairul.anuar.romli at altera.com>
>> Subject: [PATCH v3 7/7] drivers: ddr: altera: Fix Cylcone5 SPL boot loop issue
>>
>> Hardware watchdog configuration is handled correctly to resolve the SPL
>> boot loop issue on Cyclone5. When hardware watchdog is enabled, it is
>> reconfigured to make the defined timeout valid, else, making sure it is not
>> running even if it is enabled in the preloader.
>>
>> Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli at altera.com>
>> Signed-off-by: Naresh Kumar Ravulapalli
>> <nareshkumar.ravulapalli at altera.com>
>> ---
>>   drivers/ddr/altera/sdram_soc32.c | 25 ++++++++++++++++++++++++-
>>   1 file changed, 24 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/ddr/altera/sdram_soc32.c
>> b/drivers/ddr/altera/sdram_soc32.c
>> index 5cdf48d2d01..f63360f17d8 100644
>> --- a/drivers/ddr/altera/sdram_soc32.c
>> +++ b/drivers/ddr/altera/sdram_soc32.c
>> @@ -8,6 +8,10 @@
>>   #include <linux/sizes.h>
>>   #include "sdram_soc32.h"
>>   #include <watchdog.h>
>> +#include <wait_bit.h>
>> +#if !defined(CONFIG_HW_WATCHDOG)
>> +#include <asm/arch/reset_manager.h>
>> +#endif
>>
>>   DECLARE_GLOBAL_DATA_PTR;
>>
>> @@ -51,7 +55,26 @@ void sdram_init_ecc_bits(void)
>>   		memset((void *)start_addr, 0, size_init);
>>   		size -= size_init;
>>   		start_addr += size_init;
>> -		schedule();
>> +
>> +		if (IS_ENABLED(CONFIG_HW_WATCHDOG)) {
>> +			/*
>> +			 * In case the watchdog is enabled,
>> +			 * make sure to (re-)configure watchdog
>> +			 * so that the defined timeout is valid.
>> +			 */
>> +			debug("%s: %d\n", __func__, __LINE__);
>> +			hw_watchdog_init();
>> +		} else {
>> +			/*
>> +			 * If the HW watchdog is NOT enabled,
>> +			 * make sure it is not running, because
>> +			 * it is enabled in the preloader and
>> +			 * causing boot loop if is not handled.
>> +			 */
>> +			debug("%s: %d\n", __func__, __LINE__);
>> +			socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
>> +			socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
>> +		}
> 
> The legacy hw_watchdog_init() function is being removed, and the watchdog is either not used or has been migrated to the driver model framework.
> There is a risk of watchdog timeout during boot, especially in SPL when clearing large memory region.
> 
> DM for watchdog is preferred instead of legacy API, you can check how this was implemented in Agilex.
> 

Sure, will check the SoC64 code and make necessary changes.

>>   	}
>>
>>   	dcache_disable();
>> --
>> 2.35.3
> 

Kind Regards
Naresh