[PATCH v4 1/2] clk: renesas: Handle CLK_TYPE_GEN4_MDSEL in gen3_clk_get_rate64()

[Stefan Roese]

On 11.06.25 02:25, Shmuel Leib Melamud via B4 Relay wrote:
> From: Shmuel Leib Melamud <smelamud at redhat.com>
> 
> Add support of CLK_TYPE_GEN4_MDSEL clock type to gen3_clk_get_rate64()
> function. In particular, this type of clock is used by Renesas R-Car
> Gen4 watchdog. It operates similarly to CLK_TYPE_GEN3_MDSEL clock.
> 
> Signed-off-by: Shmuel Leib Melamud <smelamud at redhat.com>
> Reviewed-by: Mattijs Korpershoek <mkorpershoek at kernel.org>
> Reviewed-by: Marek Vasut <marek.vasut+renesas at mailbox.org>

Reviewed-by: Stefan Roese <sr at denx.de>

Thanks,
Stefan

> ---
>   drivers/clk/renesas/clk-rcar-gen3.c | 4 +++-
>   1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c
> index 375cc4a4930873ad0d5509c19ad04a0ea5545aa0..5745acf4023c9114f6fa13b5e4baa306c5b57d33 100644
> --- a/drivers/clk/renesas/clk-rcar-gen3.c
> +++ b/drivers/clk/renesas/clk-rcar-gen3.c
> @@ -68,7 +68,7 @@ static int gen3_clk_get_parent(struct gen3_clk_priv *priv, struct clk *clk,
>   		if (ret)
>   			return ret;
>   
> -		if (core->type == CLK_TYPE_GEN3_MDSEL) {
> +		if (core->type == CLK_TYPE_GEN3_MDSEL || core->type == CLK_TYPE_GEN4_MDSEL) {
>   			shift = priv->cpg_mode & BIT(core->offset) ? 0 : 16;
>   			parent->dev = clk->dev;
>   			parent->id = core->parent >> shift;
> @@ -318,6 +318,8 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
>   						"FIXED");
>   
>   	case CLK_TYPE_GEN3_MDSEL:
> +		fallthrough;
> +	case CLK_TYPE_GEN4_MDSEL:
>   		shift = priv->cpg_mode & BIT(core->offset) ? 0 : 16;
>   		div = (core->div >> shift) & 0xffff;
>   		rate = gen3_clk_get_rate64(&parent) / div;
> 

Viele Grüße,
Stefan Roese

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