[PATCH] Improve user feedback in case of FPGA bitstream load failure

[Pieter Van Trappen]

On 6/19/25 16:36, Tom Rini wrote:
> On Wed, Jun 18, 2025 at 09:30:24PM +0200, Pieter Van Trappen wrote:
>> On 6/18/25 18:16, Tom Rini wrote:
>>> On Wed, Jun 18, 2025 at 05:44:29PM +0200, Pieter Van Trappen wrote:
>>>> On 18/06/2025 15:57, Tom Rini wrote:
>>>>> On Wed, Jun 18, 2025 at 09:15:54AM +0200, Michal Simek wrote:
>>>>>>
>>>>>>
>>>>>> On 6/17/25 11:23, vtpieter at gmail.com wrote:
>>>>>>> From: Pieter Van Trappen <pieter.van.trappen at cern.ch>
>>>>>>> -		debug("fpga: incorrect parameters passed\n");
>>>>>>> +		puts("fpga: incorrect parameters passed\n");
>>>>>>
>>>>>> I think all of these should be moved to log_err that you should be able to
>>>>>> control verbosity.
>>>>>>
>>>>>> Tom: I think this is where you want to go right?
>>>>>
>>>>> Sounds right, thanks.
>>>>>
>>>>
>>>> Right I will amend accordingly in a v2.
>>>>
>>>> I'm trying to compile now that it's more than some tweaks and I notice many
>>>> (fixable) errors in the drivers/fpga files such as missing time.h includes,
>>>> spotted by gcc 14.2 (x86_64). I'm on the next branch.
>>>>
>>>> Is this due to my gcc being too recent or is something else going on? I
>>>> don't mind patching these in case that's welcomed; let me know.
>>>
>>> Just further changes on the next branch which your changes are exposing
>>> I guess, separate patches for them would be much appreciated, thanks!
>>>
>>
>> Thanks but that's not the case; I switched to the latest `next` HEAD which
>> is your commit ce2a7fcb and I get the same error, see below (one of many).
>> Maybe due to my config in which I enabled all FPGA-related configs? Is is
>> there a `allyesconfig` pipeline somewhere? Sorry I'm new to u-boot
>> development and I don't think patchwork is running pipelines. I'm further
>> investigating, I'm probably doing something wrong although the gcc errors
>> are correct AFAIK.
> 
> Yes, it's related to changing the configs and no we don't have an
> allyesconfig option in the pipeline. It's still somewhere on the TODO
> list as there's a lot of issues to sort out there.

OK I understand now; just wanted to make sure I'm not doing work that 
doesn't serve any purpose. I happily contribute by activating all 
FPGA-related configs and fix these compilers errors which seems rather 
straight-forward.

That'll take more time than initially anticipated; I'm hoping to submit 
patches next week.

Cheers, Pieter