[PATCH v2] usb: dwc3: qcom: Add delays in UTMI clock selection for Qscratch

[Balaji Selvanathan]

Added delays before and after setting the PIPE_UTMI_CLK_SEL and
PIPE3_PHYSTATUS_SW bits in the Qscratch GENERAL_CFG register
during UTMI clock selection for DWC3 on Qualcomm platforms.

These delays help ensure proper timing and stability of the UTMI
clock switching sequence, potentially avoiding race conditions or
unstable PHY behavior during initialization.

Tested on platforms using Qscratch-based DWC3 PHY configuration.

This change is taken from this Linux kernel implementation:
https://web.git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/usb/dwc3/dwc3-qcom.c?id=a4333c3a6ba9ca9cff50a3c1d1bf193dc5489e1c

Signed-off-by: Balaji Selvanathan <balaji.selvanathan at oss.qualcomm.com>
---
Changes in v2:
- Corrected typo in email id in Signed-off (in v1)
- Link to v1: https://lore.kernel.org/u-boot/20250627044304.2223767-1-balaji.selvanathan@oss.qualcomm.com/
---
 drivers/usb/dwc3/dwc3-generic.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index 21452ad1569..4800eb64484 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -460,9 +460,13 @@ static void dwc3_qcom_select_utmi_clk(void __iomem *qscratch_base)
 	setbits_le32(qscratch_base + QSCRATCH_GENERAL_CFG,
 			  PIPE_UTMI_CLK_DIS);
 
+	udelay(100);
+
 	setbits_le32(qscratch_base + QSCRATCH_GENERAL_CFG,
 			  PIPE_UTMI_CLK_SEL | PIPE3_PHYSTATUS_SW);
 
+	udelay(100);
+
 	clrbits_le32(qscratch_base + QSCRATCH_GENERAL_CFG,
 			  PIPE_UTMI_CLK_DIS);
 }
-- 
2.34.1