[PATCH v1 1/5] arm: socfpga: agilex5: Add MMU mapping region

[Yixun Lan]

On 06:32 Mon 21 Apr     , Chee, Tien Fong wrote:
> 
> 
> > -----Original Message-----
> > From: Meng, Tingting <tingting.meng at altera.com>
> > Sent: Monday, April 21, 2025 1:11 PM
> > To: u-boot at lists.denx.de
> > Cc: Marek Vasut <marex at denx.de>; Chee, Tien Fong
> > <tien.fong.chee at altera.com>; Meng, Tingting <tingting.meng at altera.com>;
> > Hea, Kok Kiang <kok.kiang.hea at altera.com>; Maniyam, Dinesh
> > <dinesh.maniyam at altera.com>; Ng, Boon Khai <boon.khai.ng at altera.com>;
> > Yuslaimi, Alif Zakuan <alif.zakuan.yuslaimi at altera.com>; Rosdi, Danish
> > Ahmad <danish.ahmad.rosdi at altera.com>; Zamri, Muhammad Hazim Izzat
> > <muhammad.hazim.izzat.zamri at altera.com>; Lim, Jit Loon
> > <jit.loon.lim at altera.com>
> > Subject: [PATCH v1 1/5] arm: socfpga: agilex5: Add MMU mapping region
> > 
> > From: Tingting Meng <tingting.meng at altera.com>
> > 
> > MMU mapping regions were added for the second and third DDR memory
> > banks.
> > 
> > Signed-off-by: Tingting Meng <tingting.meng at altera.com>
> > ---
> >  arch/arm/mach-socfpga/mmu-arm64_s10.c | 14 ++++++++++++++
> >  1 file changed, 14 insertions(+)
> > 
> [...]
> Reviewed-by: Tien Fong Chee <tien.fong.chee at altera.com>
> 
You can simply reply to cover letter to give all patches a Reviewed-by
(No need to do for each)

and use tools like - b4 trailers to collect

-- 
Yixun Lan (dlan)