[PATCH] riscv: set the width of the physical address/size data type based on arch

[Sughosh Ganu]

U-Boot has support for both the 32-bit and 64-bit RiscV platforms. Set
the width of the phys_{addr,size}_t data types based on the register
size of the architecture.

Currently, even the 32-bit RiscV platforms have a 64-bit
phys_{addr,size}_t data types. This causes issues on the 32-bit
platforms, where the upper 32-bits of the variables of these types
can have junk data, and that can cause all kinds of side-effects.

This was discovered on the qemu Riscv 32-bit platform  when the return
value of an LMB API was checked, and some LMB allocation that ought
not to have failed, was failing. The upper 32-bits of the address
variable contained garbage, resulting in failures.

Signed-off-by: Sughosh Ganu <sughosh.ganu at linaro.org>
---

Note:
Although the LMB API cleanup series depends on this patch, I am
sending it separately so that it gets noticed by the RiscV
maintainers. Sometimes a patch may not get the required attention when
sent as part of another seemingly unrelated series.


 arch/riscv/include/asm/types.h | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/include/asm/types.h b/arch/riscv/include/asm/types.h
index 49f7a5d6b3a..45d806c83eb 100644
--- a/arch/riscv/include/asm/types.h
+++ b/arch/riscv/include/asm/types.h
@@ -35,8 +35,13 @@ typedef u64 dma_addr_t;
 typedef u32 dma_addr_t;
 #endif
 
-typedef unsigned long long phys_addr_t;
-typedef unsigned long long phys_size_t;
+#ifdef CONFIG_PHYS_64BIT
+typedef u64 phys_addr_t;
+typedef u64 phys_size_t;
+#else
+typedef u32 phys_addr_t;
+typedef u32 phys_size_t;
+#endif
 
 #endif /* __KERNEL__ */
 
-- 
2.34.1