[PATCH 0/5] Enhance DDR support for Arria10 SoCFPGA

[Naresh Kumar Ravulapalli]

DDR driver of Arria10 SoCFPGA is enhanced in below ways:
a) Check DRAM size from device tree and actual hardware,
   mismatch is notified to the user
b) Fix a bug during computation of mpu1 address
c) Move common code specifically, initializing SDRAM ECC bits to a
   common sdram_soc32 file. This allows using the same code for
   future devices.
d) ECC scrubbing is sped up by enabling Dcache

Naresh Kumar Ravulapalli (5):
  drivers: ddr: altera: arria10: Add DRAM size checking
  drivers: ddr: altera: arria10: Add valid RAM size check
  drivers: ddr: altera: arria10: Fix incorrect address for mpu1
  drivers: ddr: altera: arria10: Move common code to common file
  drivers: ddr: altera: Add ECC scrubbing with Dcache enabled

 drivers/ddr/altera/Makefile        |   2 +-
 drivers/ddr/altera/sdram_arria10.c | 115 +++++++++++++++++------------
 drivers/ddr/altera/sdram_soc32.c   |  88 ++++++++++++++++++++++
 drivers/ddr/altera/sdram_soc32.h   |  11 +++
 4 files changed, 166 insertions(+), 50 deletions(-)
 create mode 100644 drivers/ddr/altera/sdram_soc32.c
 create mode 100644 drivers/ddr/altera/sdram_soc32.h

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2.35.3