[RFC PATCH 3/3] serial: mxc: restore booting for imx8mn_bsh_smm_s2

[Michael Nazzareno Trimarchi]

Hi Fabio

On Sat, May 17, 2025 at 10:44 PM Michael Nazzareno Trimarchi
<michael at amarulasolutions.com> wrote:
>
> Hi
>
> On Sat, May 17, 2025 at 10:28 PM Fabio Estevam <festevam at gmail.com> wrote:
> >
> > On Sat, May 17, 2025 at 5:15 PM Michael Nazzareno Trimarchi
> > <michael at amarulasolutions.com> wrote:
> >
> > > Can you please point me to an example of a tested board?
> >
> > I have just tested the top-of-tree U-Boot on an imx8mn evk board:
> >
> > U-Boot SPL 2025.07-rc2-00018-g126a88d49bca (May 17 2025 - 17:21:14 -0300)
> > WDT:   Started watchdog at 30280000 with servicing every 1000ms (60s timeout)
> > SEC0:  RNG instantiated
> > Normal Boot
> > Trying to boot from BOOTROM
> > Boot Stage: Primary boot
> > image offset 0x8000, pagesize 0x200, ivt offset 0x0
> > NOTICE:  Do not release JR0 to NS as it can be used by HAB
> > NOTICE:  BL31: v2.12.0(release):v2.12.0
> > NOTICE:  BL31: Built : 17:16:49, May 17 2025
> >
>
> I was on master except this commit
>
> commit 128d997a8772cc174f38d529d8b25f90b3aa8ad8
> Author: Jonas Karlman <jonas at kwiboo.se>
> Date:   Sat May 10 15:32:01 2025 +0000
>
>     clk: Fix clk_set_parent() regression
>
>     The commit ac30d90f3367 ("clk: Ensure the parent clocks are enabled
>     while reparenting") add a call to clk_enable() for the parent clock.
>
>     For clock drivers that do not implement the enable() ops, like most
>     Rockchip clock drivers, this now cause the set_parent() ops to never
>     be called when CLK_CCF=n (default for Rockchip).
>
>

BTW is really needed now?

git grep init_uart_clk board/freescale/imx8mn_evk/
board/freescale/imx8mn_evk/spl.c:       init_uart_clk(1);


Michael

> I can not try today but if you can, is this the commit that could break my boot?
>
> Michael
> >
> > U-Boot 2025.07-rc2-00018-g126a88d49bca (May 17 2025 - 17:21:14 -0300)
> >
> > CPU:   NXP i.MX8MNano Quad Rev1.0 A53 at 1200 MHz
> > CPU:   Consumer temperature grade (0C to 95C) at 32C
> > Model: NXP i.MX8MNano DDR4 EVK board
> > DRAM:  2 GiB
> > Core:  180 devices, 23 uclasses, devicetree: separate
> > WDT:   Started watchdog at 30280000 with servicing every 1000ms (60s timeout)
> > MMC:   FSL_SDHC: 1, FSL_SDHC: 2
> > Loading Environment from MMC... Reading from MMC(1)... OK
> > In:    serial at 30890000
> > Out:   serial at 30890000
> > Err:   serial at 30890000
> > SEC0:  RNG instantiated
> > Net:   eth0: ethernet at 30be0000
> > Hit any key to stop autoboot:  0
> > u-boot=>
> >
> > Make sure you are using the most recent U-Boot. We had some imx8m
> > clock drive hickups after 2025.04.
>
>
>
> --
> Michael Nazzareno Trimarchi
> Co-Founder & Chief Executive Officer
> M. +39 347 913 2170
> michael at amarulasolutions.com
> __________________________________
>
> Amarula Solutions BV
> Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
> T. +31 (0)85 111 9172
> info at amarulasolutions.com
> www.amarulasolutions.com



-- 
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
michael at amarulasolutions.com
__________________________________

Amarula Solutions BV
Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
T. +31 (0)85 111 9172
info at amarulasolutions.com
www.amarulasolutions.com