[PATCH v2] phy: zynqmp: Fix sgmii clk ctrl GTR lane bit shift

[Michal Simek]

On 5/21/25 20:16, Rutherther wrote:
> The bitshift in GEM_CLK_CTRL register is five bits, not two. There are
> four bits for each GEM, and one bit reserved in between.
> 
> This has caused that using more than one GEM is impossible,
> additionally corrupting the GEM0's configuration, leaving GEM0
> unusable as well (ie. if GEM0 and GEM1 are used, GEM1 configuration is
> going to write to GEM0's registers wrong value, leaving GEM0 unusable)
> 
> Signed-off-by: Frantisek Bohacek <rutherther at ditigal.xyz>

You still have the problem that address which you are using for sending is not 
matching your SOB line.
Author:     Rutherther <rutherther at ditigal.xyz>
Signed-off-by: Frantisek Bohacek <rutherther at ditigal.xyz>

You can try to apply your patch yourself and see it via git log.

Thanks,
Michal