[PATCH 2/6] arch: mach-k3: common: Add support to shutdown MCU R5 Core 1
Neha Malcom Francis
n-francis at ti.com
Thu May 22 09:51:08 CEST 2025
On 22/05/25 12:48, Beleswar Padhi wrote:
> During boot, ROM can bring up the MCU R5F cores in either lockstep or
> split mode based on X509 certificate flags. If booted in split mode,
> core 0 will run DM firmware and second core sits in WFI. Add support to
> shut down core 1 so that other firmwares can later be loaded on them.
>
> The shutdown of MCU R5 Core 1 is invoked at A72 SPL init, as by that
> time Device Manager (DM) is up and running on R5 Core 0. The shutdown
> request of Core 1 is handled by Device Manager itself.
>
> Signed-off-by: Beleswar Padhi <b-padhi at ti.com>
> ---
> arch/arm/mach-k3/common.c | 55 +++++++++++++++++++++++++++
> arch/arm/mach-k3/common.h | 1 +
> arch/arm/mach-k3/j721e/j721e_init.c | 9 ++++-
> arch/arm/mach-k3/j721s2/j721s2_init.c | 7 ++++
> arch/arm/mach-k3/j784s4/j784s4_init.c | 7 ++++
> 5 files changed, 78 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
> index fc230f180d0..68f24948134 100644
> --- a/arch/arm/mach-k3/common.c
> +++ b/arch/arm/mach-k3/common.c
> @@ -31,6 +31,10 @@
> #include <dm/uclass-internal.h>
> #include <dm/device-internal.h>
>
> +#define PROC_BOOT_CTRL_FLAG_R5_CORE_HALT 0x00000001
> +#define PROC_ID_MCU_R5FSS0_CORE1 0x02
> +#define PROC_BOOT_CFG_FLAG_R5_LOCKSTEP 0x00000100
> +
> #include <asm/arch/k3-qos.h>
>
> struct ti_sci_handle *get_ti_sci_handle(void)
> @@ -328,3 +332,54 @@ void setup_qos(void)
> writel(qos_data[i].val, (uintptr_t)qos_data[i].reg);
> }
> #endif
> +
> +int shutdown_mcu_r5_core1(void)
> +{
Better to build this function only if CONFIG_ARM64 is enabled?
> + struct ti_sci_handle *ti_sci = get_ti_sci_handle();
> + struct ti_sci_dev_ops *dev_ops = &ti_sci->ops.dev_ops;
> + struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops;
> + u32 dev_id_mcu_r5_core1 = put_core_ids[0];
> + u64 boot_vector;
> + u32 cfg, ctrl, sts;
> + int cluster_mode_lockstep, ret;
> +
> + ret = proc_ops->proc_request(ti_sci, PROC_ID_MCU_R5FSS0_CORE1);
> + if (ret) {
> + printf("Unable to request processor control for core %d\n",
> + PROC_ID_MCU_R5FSS0_CORE1);
> + return ret;
> + }
> +
> + ret = proc_ops->get_proc_boot_status(ti_sci, PROC_ID_MCU_R5FSS0_CORE1,
> + &boot_vector, &cfg, &ctrl, &sts);
> + if (ret) {
> + printf("Unable to get Processor boot status for core %d\n",
> + PROC_ID_MCU_R5FSS0_CORE1);
> + goto release_proc_ctrl;
> + }
> +
> + /* Shutdown MCU R5F Core 1 only if the cluster is booted in SplitMode */
> + cluster_mode_lockstep = !!(cfg & PROC_BOOT_CFG_FLAG_R5_LOCKSTEP);
> + if (cluster_mode_lockstep) {
> + ret = -EINVAL;
> + goto release_proc_ctrl;
> + }
> +
> + ret = proc_ops->set_proc_boot_ctrl(ti_sci, PROC_ID_MCU_R5FSS0_CORE1,
> + PROC_BOOT_CTRL_FLAG_R5_CORE_HALT, 0);
> + if (ret) {
> + printf("Unable to Halt core %d\n", PROC_ID_MCU_R5FSS0_CORE1);
> + goto release_proc_ctrl;
> + }
> +
> + ret = dev_ops->put_device(ti_sci, dev_id_mcu_r5_core1);
> + if (ret) {
> + printf("Unable to assert reset on core %d\n",
> + PROC_ID_MCU_R5FSS0_CORE1);
> + return ret;
> + }
> +
> +release_proc_ctrl:
> + proc_ops->proc_release(ti_sci, PROC_ID_MCU_R5FSS0_CORE1);
> + return ret;
> +}
> diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h
> index 02c74731fea..6e33f578151 100644
> --- a/arch/arm/mach-k3/common.h
> +++ b/arch/arm/mach-k3/common.h
> @@ -49,6 +49,7 @@ enum k3_device_type get_device_type(void);
> struct ti_sci_handle *get_ti_sci_handle(void);
> void do_board_detect(void);
> void ti_secure_image_check_binary(void **p_image, size_t *p_size);
> +int shutdown_mcu_r5_core1(void);
>
> #if (IS_ENABLED(CONFIG_K3_QOS))
> void setup_qos(void);
> diff --git a/arch/arm/mach-k3/j721e/j721e_init.c b/arch/arm/mach-k3/j721e/j721e_init.c
> index f31c20f7ed6..edca2634fb9 100644
> --- a/arch/arm/mach-k3/j721e/j721e_init.c
> +++ b/arch/arm/mach-k3/j721e/j721e_init.c
> @@ -296,9 +296,9 @@ void do_dt_magic(void)
>
> void board_init_f(ulong dummy)
> {
> + int ret;
> #if defined(CONFIG_K3_J721E_DDRSS) || defined(CONFIG_K3_LOAD_SYSFW)
> struct udevice *dev;
> - int ret;
> #endif
> /*
> * Cannot delay this further as there is a chance that
> @@ -371,6 +371,13 @@ void board_init_f(ulong dummy)
> preloader_console_init();
> #endif
>
> + /* Shutdown MCU_R5 Core 1 in Split mode at A72 SPL Stage */
> + if (IS_ENABLED(CONFIG_ARM64)) {
> + ret = shutdown_mcu_r5_core1();
> + if (ret)
> + printf("Unable to shutdown MCU R5 core 1, %d\n", ret);
> + }
> +
> /* Output System Firmware version info */
> k3_sysfw_print_ver();
>
> diff --git a/arch/arm/mach-k3/j721s2/j721s2_init.c b/arch/arm/mach-k3/j721s2/j721s2_init.c
> index 5941fa26a95..6342161f830 100644
> --- a/arch/arm/mach-k3/j721s2/j721s2_init.c
> +++ b/arch/arm/mach-k3/j721s2/j721s2_init.c
> @@ -230,6 +230,13 @@ void k3_spl_init(void)
> remove_fwl_configs(navss_cbass0_fwls, ARRAY_SIZE(navss_cbass0_fwls));
> }
>
> + /* Shutdown MCU_R5 Core 1 in Split mode at A72 SPL Stage */
> + if (IS_ENABLED(CONFIG_ARM64)) {
> + ret = shutdown_mcu_r5_core1();
> + if (ret)
> + printf("Unable to shutdown MCU R5 core 1, %d\n", ret);
> + }
> +
> /* Output System Firmware version info */
> k3_sysfw_print_ver();
> }
> diff --git a/arch/arm/mach-k3/j784s4/j784s4_init.c b/arch/arm/mach-k3/j784s4/j784s4_init.c
> index 787cf6261e4..2756accbe12 100644
> --- a/arch/arm/mach-k3/j784s4/j784s4_init.c
> +++ b/arch/arm/mach-k3/j784s4/j784s4_init.c
> @@ -206,6 +206,13 @@ void k3_spl_init(void)
>
> writel(AUDIO_REFCLK1_DEFAULT, (uintptr_t)CTRL_MMR_CFG0_AUDIO_REFCLK1_CTRL);
>
> + /* Shutdown MCU_R5 Core 1 in Split mode at A72 SPL Stage */
> + if (IS_ENABLED(CONFIG_ARM64)) {
> + ret = shutdown_mcu_r5_core1();
> + if (ret)
> + printf("Unable to shutdown MCU R5 core 1, %d\n", ret);
> + }
> +
> /* Output System Firmware version info */
> k3_sysfw_print_ver();
> }
--
Thanking You
Neha Malcom Francis
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