[PATCH v4 04/28] clk: qcom: Support uart clk on sc7280 CRD

[Stephen Boyd]

Support setting the frequency of the UART clk on sc7280 so that the
serial console works on devices like hoglin.

Signed-off-by: Stephen Boyd <swboyd at chromium.org>
---
 drivers/clk/qcom/clock-sc7280.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/drivers/clk/qcom/clock-sc7280.c b/drivers/clk/qcom/clock-sc7280.c
index 9aff8a847ad1..b9152c129df1 100644
--- a/drivers/clk/qcom/clock-sc7280.c
+++ b/drivers/clk/qcom/clock-sc7280.c
@@ -38,6 +38,22 @@ static const struct freq_tbl ftbl_gcc_usb30_sec_master_clk_src[] = {
 	{ }
 };
 
+static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s2_clk_src[] = {
+        F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625),
+        F(14745600, CFG_CLK_SRC_GPLL0_EVEN, 1, 768, 15625),
+        F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
+        F(29491200, CFG_CLK_SRC_GPLL0_EVEN, 1, 1536, 15625),
+        F(32000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 75),
+        F(48000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 25),
+        F(52174000, CFG_CLK_SRC_GPLL0, 1, 2, 23),
+        F(64000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 16, 75),
+        F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0),
+        F(80000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 15),
+        F(96000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 25),
+        F(100000000, CFG_CLK_SRC_GPLL0, 6, 0, 0),
+        { }
+};
+
 static ulong sc7280_set_rate(struct clk *clk, ulong rate)
 {
 	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
@@ -47,6 +63,11 @@ static ulong sc7280_set_rate(struct clk *clk, ulong rate)
 		debug("%s: %s, requested rate=%ld\n", __func__, priv->data->clks[clk->id].name, rate);
 
 	switch (clk->id) {
+	case GCC_QUPV3_WRAP0_S5_CLK: /* UART5 */
+		freq = qcom_find_freq(ftbl_gcc_qupv3_wrap0_s2_clk_src, rate);
+		clk_rcg_set_rate_mnd(priv->base, 0x17600,
+				     freq->pre_div, freq->m, freq->n, freq->src, 16);
+		return freq->freq;
 	case GCC_USB30_PRIM_MASTER_CLK:
 		freq = qcom_find_freq(ftbl_gcc_usb30_prim_master_clk_src, rate);
 		clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR,
@@ -107,6 +128,7 @@ static const struct gate_clk sc7280_clks[] = {
 	GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x52008, BIT(10)),
 	GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x52008, BIT(11)),
 	GATE_CLK(GCC_QUPV3_WRAP0_S3_CLK, 0x52008, BIT(13)),
+	GATE_CLK(GCC_QUPV3_WRAP0_S5_CLK, 0x52008, BIT(15)),
 	GATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x77010, BIT(0)),
 	GATE_CLK(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x770cc, BIT(0)),
 	GATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x77018, BIT(0)),
-- 
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