[PATCH 6/7] ARM: dts: Add RV1103 Omega4 support
Fabio Estevam
festevam at gmail.com
Sun Feb 1 01:44:55 CET 2026
From: Fabio Estevam <festevam at nabladev.com>
Add minimal devicetree support for the Onion RV1103 Omega4 board.
These devicetrees are currently not upstream in Linux. They allow U-Boot to
boot the board and progress with development, independent of the Linux RV1103
upstream process.
Once the RV1103 devicetrees are merged into the upstream Linux kernel,
he OF_UPSTREAM mechanism can be enabled to use the kernel-provided devicetree.
This patch enables the Onion's Omega4 board to be supported in U-Boot
without blocking other upstreaming efforts.
Signed-off-by: Fabio Estevam <festevam at nabladev.com>
---
arch/arm/dts/rv1103-omega4-u-boot.dtsi | 11 +
arch/arm/dts/rv1103-omega4.dts | 40 ++++
arch/arm/dts/rv1103-u-boot.dtsi | 4 +
arch/arm/dts/rv1103.dtsi | 267 +++++++++++++++++++++++++
4 files changed, 322 insertions(+)
create mode 100644 arch/arm/dts/rv1103-omega4-u-boot.dtsi
create mode 100644 arch/arm/dts/rv1103-omega4.dts
create mode 100644 arch/arm/dts/rv1103-u-boot.dtsi
create mode 100644 arch/arm/dts/rv1103.dtsi
diff --git a/arch/arm/dts/rv1103-omega4-u-boot.dtsi b/arch/arm/dts/rv1103-omega4-u-boot.dtsi
new file mode 100644
index 000000000000..d838206af4af
--- /dev/null
+++ b/arch/arm/dts/rv1103-omega4-u-boot.dtsi
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0+
+// (C) Copyright 2024 Rockchip Electronics Co., Ltd
+
+#include "rockchip-u-boot.dtsi"
+
+/ {
+ chosen {
+ stdout-path = &uart0;
+ u-boot,spl-boot-order = &spi_nand;
+ };
+};
diff --git a/arch/arm/dts/rv1103-omega4.dts b/arch/arm/dts/rv1103-omega4.dts
new file mode 100644
index 000000000000..ebedf9843934
--- /dev/null
+++ b/arch/arm/dts/rv1103-omega4.dts
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0+
+// (C) Copyright 2024 Rockchip Electronics Co., Ltd
+
+/dts-v1/;
+#include "rv1103.dtsi"
+
+/ {
+ model = "Onion RV1103 Omega4 board";
+ compatible = "onion,rv1103-omega4", "rockchip,rv1103";
+
+ chosen {
+ stdout-path = &uart0;
+ };
+};
+
+&sfc {
+ bootph-all;
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ spi_nand: flash at 0 {
+ compatible = "spi-nand";
+ reg = <0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <24000000>;
+ bootph-all;
+ };
+};
+
+&uart0 {
+ bootph-pre-ram;
+ status = "okay";
+};
+
+&wdt {
+ bootph-pre-ram;
+ status = "okay";
+};
diff --git a/arch/arm/dts/rv1103-u-boot.dtsi b/arch/arm/dts/rv1103-u-boot.dtsi
new file mode 100644
index 000000000000..3b77dd31152f
--- /dev/null
+++ b/arch/arm/dts/rv1103-u-boot.dtsi
@@ -0,0 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
+// (C) Copyright 2024 Rockchip Electronics Co., Ltd
+
+#include "rockchip-u-boot.dtsi"
diff --git a/arch/arm/dts/rv1103.dtsi b/arch/arm/dts/rv1103.dtsi
new file mode 100644
index 000000000000..8ac7658231b1
--- /dev/null
+++ b/arch/arm/dts/rv1103.dtsi
@@ -0,0 +1,267 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ */
+
+#include <dt-bindings/clock/rv1103-cru.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ compatible = "rockchip,rv1103";
+
+ interrupt-parent = <&gic>;
+
+ aliases {
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ };
+
+ arm-pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu at 0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x0>;
+ clocks = <&cru ARMCLK>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
+ clock-frequency = <24000000>;
+ };
+
+ cru: clock-controller at 20000000 {
+ compatible = "rockchip,rv1103-cru";
+ reg = <0x20000000 0x81000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ assigned-clocks = <&cru PLL_GPLL>, <&cru CLK_GPLL_DIV12>;
+ assigned-clock-rates = <1188000000>, <100000000>;
+ bootph-all;
+ };
+
+ grf: syscon at 20100000 {
+ compatible = "rockchip,rv1103-grf", "syscon", "simple-mfd";
+ reg = <0x20100000 0x61000>;
+ bootph-all;
+ };
+
+ ioc: syscon at 20170000 {
+ compatible = "rockchip,rv1103-ioc", "syscon";
+ reg = <0x20170000 0x60000>;
+ bootph-all;
+ };
+
+ gic: interrupt-controller at 20411000 {
+ compatible = "arm,gic-400";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+
+ reg = <0x20411000 0x1000>,
+ <0x20412000 0x2000>,
+ <0x20414000 0x2000>,
+ <0x20416000 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ uart0: serial at 20540000 {
+ compatible = "rockchip,rv1103-uart", "snps,dw-apb-uart";
+ reg = <0x20540000 0x100>;
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
+ clock-names = "baudclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0m0_xfer_pins>;
+ status = "disabled";
+ };
+
+ uart1: serial at 20870000 {
+ compatible = "rockchip,rv1103-uart", "snps,dw-apb-uart";
+ reg = <0x20870000 0x100>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
+ clock-names = "baudclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1m0_xfer_pins>;
+ status = "disabled";
+ };
+
+ uart2: serial at 20880000 {
+ compatible = "rockchip,rv1103-uart", "snps,dw-apb-uart";
+ reg = <0x20880000 0x100>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
+ clock-names = "baudclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2m0_xfer_pins>;
+ status = "disabled";
+ };
+
+ wdt: watchdog at 208d0000 {
+ compatible = "rockchip,rv1103-wdt", "snps,dw-wdt";
+ reg = <0x208d0000 0x100>;
+ clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>;
+ clock-names = "tclk", "pclk";
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ sfc: spi at 20d40000 {
+ compatible = "rockchip,sfc";
+ reg = <0x20d40000 0x4000>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_SFC_2X>, <&cru HCLK_SFC>;
+ clock-names = "clk_sfc", "hclk_sfc";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ system_sram: sram at 210f6000 {
+ compatible = "mmio-sram";
+ reg = <0x210f6000 0x8000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x210f6000 0x8000>;
+ };
+
+ pinctrl: pinctrl {
+ compatible = "rockchip,rv1103-pinctrl";
+ rockchip,grf = <&ioc>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ bootph-all;
+
+ gpio0: gpio at 20520000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x20520000 0x200>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_PMU_GPIO0>, <&cru DBCLK_PMU_GPIO0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 0 32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ bootph-pre-ram;
+ };
+
+ gpio1: gpio at 20d80000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x20d80000 0x200>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 32 32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ bootph-pre-ram;
+ };
+
+ gpio2: gpio at 20840000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x20840000 0x200>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 64 32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ bootph-pre-ram;
+ };
+
+ pcfg_pull_none: pcfg-pull-none {
+ bias-disable;
+ };
+
+ pcfg_pull_up: pcfg-pull-up {
+ bias-pull-up;
+ };
+
+ spi0 {
+ spi0m0_clk_pins: spi0m0-clk-pins {
+ rockchip,pins =
+ /* spi0_clk_m0 */
+ <2 RK_PB0 2 &pcfg_pull_none>,
+ /* spi0_miso_m0 */
+ <2 RK_PB3 2 &pcfg_pull_none>,
+ /* spi0_mosi_m0 */
+ <2 RK_PB1 2 &pcfg_pull_none>;
+ };
+
+ spi0m0_cs0_pins: spi0m0-cs0-pins {
+ rockchip,pins =
+ /* spi0_cs0n_m0 */
+ <2 RK_PB2 2 &pcfg_pull_none>;
+ };
+
+ spi0m0_cs1_pins: spi0m0-cs1-pins {
+ rockchip,pins =
+ /* spi0_cs1n_m0 */
+ <2 RK_PA7 2 &pcfg_pull_none>;
+ };
+ };
+
+ uart0 {
+ uart0m0_xfer_pins: uart0m0-xfer-pins {
+ rockchip,pins =
+ /* uart0_rx_m0 */
+ <0 RK_PA6 1 &pcfg_pull_up>,
+ /* uart0_tx_m0 */
+ <0 RK_PA5 1 &pcfg_pull_up>;
+ };
+ };
+
+ uart1 {
+ uart1m0_xfer_pins: uart1m0-xfer-pins {
+ rockchip,pins =
+ /* uart1_rx_m0 */
+ <0 RK_PB2 2 &pcfg_pull_up>,
+ /* uart1_tx_m0 */
+ <0 RK_PB3 2 &pcfg_pull_up>;
+ };
+ };
+
+ uart2 {
+ uart2m0_xfer_pins: uart2m0-xfer-pins {
+ rockchip,pins =
+ /* uart2_rx_m0 */
+ <0 RK_PB1 2 &pcfg_pull_up>,
+ /* uart2_tx_m0 */
+ <0 RK_PB0 2 &pcfg_pull_up>;
+ };
+ };
+ };
+};
--
2.34.1
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