[PATCH] spl: Ensure final section before BSS is non-empty

[Sune Brian]

On Sat, Jan 31, 2026 at 2:36 AM Tom Rini <trini at konsulko.com> wrote:
>
> As part of ensuring that we make a binary image to append our device
> tree to and that it will have an 8 byte alignment, one problem was
> overlooked. That problem is what happens when we have a section that
> only contains ALIGN statements and linker references, but nothing else.
> What happens in this case is that we will have a section in the
> resulting ELF that has is of the NOBITS type. This in turn means that
> when we use objcopy to turn the ELF in to a binary for further
> processing, it won't copy anything. This then becomes a problem when we
> do not have a separate BSS and instead append a "padding" file to act as
> the BSS, and then append our device tree to that. The solution here is
> to ensure that the final section in our SPL image is something that will
> always exist with contents, in this case __u_boot_list.
>
> Fixes: 5ffc1dcc26d3 ("arm: Remove rel.dyn from SPL linker scripts")
> Fixes: f150843499b3 ("riscv: Update linker scripts to ensure appended device tree is aligned")
> Reported-by: Brian Sune <briansune at gmail.com>
> Signed-off-by: Tom Rini <trini at konsulko.com>
> ---
> Ilias, if there's anyone else you can get to look at this which
> understands linker scripts better please do. I think I finally see *how*
> things go wrong in some cases but I'm less confident in my explanation
> above. Thanks.
>
> Cc: Ilias Apalodimas <ilias.apalodimas at linaro.org>
> ---
>  arch/arm/cpu/armv8/u-boot-spl.lds           | 12 ++++++------
>  arch/arm/cpu/u-boot-spl.lds                 | 10 +++++-----
>  arch/arm/mach-aspeed/ast2600/u-boot-spl.lds | 10 +++++-----
>  arch/riscv/cpu/u-boot-spl.lds               | 11 +++++------
>  4 files changed, 21 insertions(+), 22 deletions(-)
>
> diff --git a/arch/arm/cpu/armv8/u-boot-spl.lds b/arch/arm/cpu/armv8/u-boot-spl.lds
> index b732133ce76d..29252d870f91 100644
> --- a/arch/arm/cpu/armv8/u-boot-spl.lds
> +++ b/arch/arm/cpu/armv8/u-boot-spl.lds
> @@ -49,12 +49,6 @@ SECTIONS
>         } >.sram
>  #endif
>
> -       __u_boot_list : {
> -               . = ALIGN(8);
> -               KEEP(*(SORT(__u_boot_list*)));
> -               . = ALIGN(8);
> -       } >.sram
> -
>         .binman_sym_table : {
>                 . = ALIGN(8);
>                 __binman_sym_start = .;
> @@ -63,6 +57,12 @@ SECTIONS
>                 . = ALIGN(8);
>         } > .sram
>
> +       __u_boot_list : {
> +               . = ALIGN(8);
> +               KEEP(*(SORT(__u_boot_list*)));
> +               . = ALIGN(8);
> +       } >.sram
> +
>         __image_copy_end = .;
>         _end = .;
>         _image_binary_end = .;
> diff --git a/arch/arm/cpu/u-boot-spl.lds b/arch/arm/cpu/u-boot-spl.lds
> index c578c3ebf821..5f807323f856 100644
> --- a/arch/arm/cpu/u-boot-spl.lds
> +++ b/arch/arm/cpu/u-boot-spl.lds
> @@ -31,16 +31,16 @@ SECTIONS
>                 *(.data*)
>         }
>
> -       . = ALIGN(4);
> -       __u_boot_list : {
> -               KEEP(*(SORT(__u_boot_list*)));
> -       }
> -
>         . = ALIGN(4);
>         .binman_sym_table : {
>                 __binman_sym_start = .;
>                 KEEP(*(SORT(.binman_sym*)));
>                 __binman_sym_end = .;
> +       }
> +
> +       . = ALIGN(4);
> +       __u_boot_list : {
> +               KEEP(*(SORT(__u_boot_list*)));
>                 . = ALIGN(8);
>         }

For ARM v7 on SoCFPGA GEN5 Cyclone V boards:
AC550
AC501

Tested-by: Brian Sune <briansune at gmail.com>

>
> diff --git a/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds b/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds
> index 303ace2f61ca..260a0a79dd0a 100644
> --- a/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds
> +++ b/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds
> @@ -39,16 +39,16 @@ SECTIONS
>                 *(.data*)
>         } > .nor
>
> -       . = ALIGN(4);
> -       __u_boot_list : {
> -               KEEP(*(SORT(__u_boot_list*)));
> -       } > .nor
> -
>         . = ALIGN(4);
>         .binman_sym_table : {
>                 __binman_sym_start = .;
>                 KEEP(*(SORT(.binman_sym*)));
>                 __binman_sym_end = .;
> +       } > .nor
> +
> +       . = ALIGN(4);
> +       __u_boot_list : {
> +               KEEP(*(SORT(__u_boot_list*)));
>                 . = ALIGN(8);
>         } > .nor
>
> diff --git a/arch/riscv/cpu/u-boot-spl.lds b/arch/riscv/cpu/u-boot-spl.lds
> index 35de28db8f3a..5a65e6653f25 100644
> --- a/arch/riscv/cpu/u-boot-spl.lds
> +++ b/arch/riscv/cpu/u-boot-spl.lds
> @@ -31,18 +31,17 @@ SECTIONS
>         .data : {
>                 *(.data*)
>         } > .spl_mem
> -       . = ALIGN(4);
> -
> -       __u_boot_list : {
> -               KEEP(*(SORT(__u_boot_list*)));
> -       } > .spl_mem
>
>         . = ALIGN(4);
> -
>         .binman_sym_table : {
>                 __binman_sym_start = .;
>                 KEEP(*(SORT(.binman_sym*)));
>                 __binman_sym_end = .;
> +       } > .spl_mem
> +
> +       . = ALIGN(4);
> +       __u_boot_list : {
> +               KEEP(*(SORT(__u_boot_list*)));
>                 . = ALIGN(8);
>         } > .spl_mem
>
> --
> 2.43.0
>