[PATCH 2/2] Fix x86 baytrail boot flow, UPD/VPD Updates
Simon Glass
sjg at chromium.org
Tue Feb 3 22:29:36 CET 2026
Hi,
On Wed, 4 Feb 2026 at 07:14, Tom Rini <trini at konsulko.com> wrote:
>
> On Mon, Jul 14, 2025 at 04:02:49PM -0500, Eric Schikschneit wrote:
>
> > The VPD has been updated to include additional values found in the Intel
> > FSP_MR5 Integration Guide.
> >
> > Disable MRC_CACHE for the baytrail platform as this will break the boot flow
> > as well. This issue has not been diagnosed further, but I suspect it is similar
> > to my previous patch and related to how modern GCC generates the low level
> > op-codes.
> >
> > Patch 2 of 2
> >
> > Upstream-Status: Pending
> >
> > Signed-off-by: Eric Schikschneit <eric.schikschneit at novatechautomation.com>
> [snip]
> > + /* Set all values to known good defaults as documented in *
> > + * Intel FSP_MR5 file: BAYTRAIL_FSP.bsf */
> > +
> > + /* NOTE: This breaks u-boot ability to set board options via *
> > + * device tree, but guarantees specific known values.. *
> > + * you wouldnt use an uninitialized variable would you?? */
>
> /*
> * Multi-line comments like this please per
> * https://docs.u-boot.org/en/latest/develop/codingstyle.html
> */
>
> And we should spell out that device tree can't set these any more in the
> commit message, along with spelling out why we can't do that anymore
> safely (why can't we?). Thanks.
Again I am not seeing this problem with minnowmax, so would like a few
more details.
Regards,
Simon
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