[PATCH v1 3/4] pwm: tegra: fix pulse_width calculation

[Svyatoslav Ryhel]

From: Jonas Schwöbel <jonasschwoebel at yahoo.de>

The pulse_width is expressed as N/256. A 100% duty cycle is only possible
when multiplied by 256 instead of 255.

Signed-off-by: Jonas Schwöbel <jonasschwoebel at yahoo.de>
Signed-off-by: Svyatoslav Ryhel <clamor95 at gmail.com>
---
 drivers/pwm/tegra_pwm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pwm/tegra_pwm.c b/drivers/pwm/tegra_pwm.c
index 3d398490408..6ddaf626dc4 100644
--- a/drivers/pwm/tegra_pwm.c
+++ b/drivers/pwm/tegra_pwm.c
@@ -39,7 +39,7 @@ static int tegra_pwm_set_config(struct udevice *dev, uint channel,
 		return -EINVAL;
 	debug("%s: Configure '%s' channel %u\n", __func__, dev->name, channel);
 
-	pulse_width = duty_ns * 255 / period_ns;
+	pulse_width = duty_ns * 256 / period_ns;
 
 	if (priv->polarity & BIT(channel))
 		pulse_width = 256 - pulse_width;
-- 
2.51.0