[PATCH] socfpga: agilex: fix NAND clock handling

[Chee, Tien Fong]

On 3/2/2026 3:56 pm, dinesh.maniyam at altera.com wrote:
> From: Dinesh Maniyam<dinesh.maniyam at altera.com>
>
> In v2025.10, the Agilex clock driver was updated to support
> clk_enable() and clk_disable() using clock-ID based bitmasks.
> However, only AGILEX_NAND_CLK was implemented, while the NAND DT
> node still referenced both nand and nand_x clocks.
>
> Since AGILEX_NAND_X_CLK is not defined in the clock driver or the
> clock-ID specification, clk_enable() failed during NAND probe.
> As a result, the Denali NAND controller never completed
> initialization.
>
> Fix this by mapping the NAND X clock to the existing l4_mp clock
> bitmask, aligning the DT expectations with the clock driver and
> restoring proper NAND controller initialization.
>
> Signed-off-by: Dinesh Maniyam<dinesh.maniyam at altera.com>
> ---
>   drivers/clk/altera/clk-agilex.c | 1 +
>   1 file changed, 1 insertion(+)
>
> diff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c
> index fdbf834bb2f..f1e2fded7d4 100644
> --- a/drivers/clk/altera/clk-agilex.c
> +++ b/drivers/clk/altera/clk-agilex.c
> @@ -657,6 +657,7 @@ static int bitmask_from_clk_id(struct clk *clk)
>   		plat->bitmask = CLKMGR_MAINPLLGRP_EN_L4MAINCLK_MASK;
>   		break;
>   	case AGILEX_L4_MP_CLK:
> +	case AGILEX_NAND_X_CLK:
>   		plat->pllgrp = CLKMGR_MAINPLL_EN;
>   		plat->bitmask = CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK;
>   		break;

Reviewed-by: Tien Fong Chee <tien.fong.chee at altera.com>

Best regards, Tien Fong