[PATCH 1/3] clk: qcom: qcs615: Add GCC_USB3_PRIM_CLKREF_CLK support

[Sumit Garg]

On Fri, Feb 13, 2026 at 02:31:18PM +0530, Balaji Selvanathan wrote:
> Add support for GCC_USB3_PRIM_CLKREF_CLK to the QCS615 clock driver.
> This clock is referenced in the device tree USB node but was not
> implemented in U-Boot, causing "Clock 152 not found" warnings during
> fastboot run.
> 
> Signed-off-by: Balaji Selvanathan <balaji.selvanathan at oss.qualcomm.com>
> ---
> Changes in v3:
> - Add support for GCC_USB3_PRIM_CLKREF_CLK to the QCS615 clock driver.
> - Removed the logic of removing GCC_USB3_PRIM_CLKREF_CLK from DTS node
> 
> Changes in v2:
> - No changes in v2
> ---
>  drivers/clk/qcom/clock-qcs615.c | 1 +
>  1 file changed, 1 insertion(+)
>

Reviewed-by: Sumit Garg <sumit.garg at oss.qualcomm.com>

-Sumit

> diff --git a/drivers/clk/qcom/clock-qcs615.c b/drivers/clk/qcom/clock-qcs615.c
> index 4700baba8c9..65b8db04020 100644
> --- a/drivers/clk/qcom/clock-qcs615.c
> +++ b/drivers/clk/qcom/clock-qcs615.c
> @@ -66,6 +66,7 @@ static const struct gate_clk qcs615_clks[] = {
>  	GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0xf050, BIT(0)),
>  	GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0xf054, BIT(0)),
>  	GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0xf058, BIT(0)),
> +	GATE_CLK(GCC_USB3_PRIM_CLKREF_CLK, 0x8c014, BIT(0)),
>  	GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x5200c, GCC_QUPV3_WRAP0_S0_CLK_ENA_BIT),
>  	GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x5200c, GCC_QUPV3_WRAP0_S1_CLK_ENA_BIT),
>  	GATE_CLK(GCC_QUPV3_WRAP0_S2_CLK, 0x5200c, GCC_QUPV3_WRAP0_S2_CLK_ENA_BIT),
> 
> -- 
> 2.34.1
>