[PATCH v5 04/10] configs: j784s4_evm_r5_defconfig: Enable configs for PCIe boot

[Kumar, Udit]

On 2/16/2026 3:58 PM, Siddharth Vadapalli wrote:
> From: Hrushikesh Salunke <h-salunke at ti.com>
>
> J784S4 SoC has two instances of PCIe, namely PCIe0 and PCIe1. The
> PCIe1 instance is used for PCIe endpoint boot. Enable the configs
> required for PCIe boot on the J784S4 platform.
>
> Additionally, enable configs for J721E WIZ SERDES wrapper, Cadence
> Torrent PHY, and MMIO multiplexer. These are required to configure
> the SERDES lanes at the R5 SPL stage for PCIe endpoint operation.
>
> Signed-off-by: Hrushikesh Salunke <h-salunke at ti.com>
> Signed-off-by: Siddharth Vadapalli <s-vadapalli at ti.com>
> ---
>   configs/j784s4_evm_r5_defconfig | 13 +++++++++++++
>   1 file changed, 13 insertions(+)

Reviewed-by: Udit Kumar <u-kumar1 at ti.com>


> diff --git a/configs/j784s4_evm_r5_defconfig b/configs/j784s4_evm_r5_defconfig
> index 25ab6f17d17..4462e7530e4 100644
> --- a/configs/j784s4_evm_r5_defconfig
> +++ b/configs/j784s4_evm_r5_defconfig
> [..]