[PATCH] arch: arm: dts: k3-r5: Drop a53_0 clock overrides in board files

[Bryan Brattlof]

On February 19, 2026 thus sayeth Anshul Dalal:
> On Thu Feb 19, 2026 at 3:57 PM IST, Wadim Egorov wrote:
> > The a53_0 clock properties are already set correctly in their
> > common k3-<soc>-r5.dtsi includes. Stop overriding them in
> > the r5 board device trees.
> >
> > Fixes the following error message:
> >   Failed to set clock rates for '/a53 at 0': -61
> >
> > Signed-off-by: Wadim Egorov <w.egorov at phytec.de>
> > ---
> >  arch/arm/dts/k3-am625-r5-phycore-som-2gb.dts  | 5 -----
> >  arch/arm/dts/k3-am625-verdin-r5.dts           | 1 -
> >  arch/arm/dts/k3-am62a7-r5-phycore-som-2gb.dts | 5 -----
> >  arch/arm/dts/k3-am642-r5-phycore-som-2gb.dts  | 5 -----
> >  4 files changed, 16 deletions(-)
> >
> > diff --git a/arch/arm/dts/k3-am625-r5-phycore-som-2gb.dts b/arch/arm/dts/k3-am625-r5-phycore-som-2gb.dts
> > index 46b621242b5..ac6f1022a55 100644
> > --- a/arch/arm/dts/k3-am625-r5-phycore-som-2gb.dts
> > +++ b/arch/arm/dts/k3-am625-r5-phycore-som-2gb.dts
> > @@ -21,11 +21,6 @@
> >  	};
> >  };
> >  
> > -&a53_0 {
> > -	clock-names = "gtc";
> > -	clocks = <&k3_clks 61 0>;
> > -};
> > -
> >  &main_pktdma {
> >  	ti,sci = <&dm_tifs>;
> >  };
> > diff --git a/arch/arm/dts/k3-am625-verdin-r5.dts b/arch/arm/dts/k3-am625-verdin-r5.dts
> > index dfd960aaf3c..971bb752052 100644
> > --- a/arch/arm/dts/k3-am625-verdin-r5.dts
> > +++ b/arch/arm/dts/k3-am625-verdin-r5.dts
> > @@ -24,7 +24,6 @@
> >  };
> >  
> >  &a53_0 {
> > -	clocks = <&k3_clks 61 0>;
> >  	/*
> >  	 * FIXME: Currently only the SPL running on the R5 has a clock
> >  	 * driver. As a workaround therefore move the assigned-clock
> 
> I wonder if there could be a better way to handle the hacky solution we
> have here and in k3-am62p5-verdin-r5 to configure the clocks for
> ETH_25MHz_CLK. Though that's a discussion for a separate patch, what we
> have here looks good to me.

There is but it will require us to re-think some things. The R5 SPL 
(before DM firmware is loaded) must use essentially a bare metal like, 
and very minimal, clk and lpsc driver before it can load DM along with 
the rest of the main domain binaries in the tispl[0]

The original idea was it could remain small enough for everyone to use 
regardless of board. As things have progressed though we have needed to 
modify the reset defaults[1], like we're doing here, or even configure 
different uarts[2] on other platforms if needed. 

It's hard to keep increasing this tree though and still fit in the limited 
sram space. Maybe we should look into allowing the /board folder to 
override this clock and power tree if needed? IDK if that helps anything.

Reviewed-by: Bryan Brattlof <bb at ti.com>

[0] http://source.denx.de/u-boot/u-boot/-/blob/master/arch/arm/mach-k3/r5/am62ax/clk-data.c
[1] https://lore.kernel.org/u-boot/20260128123623.2737451-1-s-vadapalli@ti.com/
[2] https://github.com/beagleboard/u-boot/commit/c6678d3338ac2b8429028b5b36c6096761531142

~Bryan

> 
> Thanks for the cleanup,
> Reviewed-by: Anshul Dalal <anshuld at ti.com>
> 
> > diff --git a/arch/arm/dts/k3-am62a7-r5-phycore-som-2gb.dts b/arch/arm/dts/k3-am62a7-r5-phycore-som-2gb.dts
> > index b54cd9d48a4..c949485017e 100644
> > --- a/arch/arm/dts/k3-am62a7-r5-phycore-som-2gb.dts
> > +++ b/arch/arm/dts/k3-am62a7-r5-phycore-som-2gb.dts
> > @@ -22,11 +22,6 @@
> >  	};
> >  };
> >  
> > -&a53_0 {
> > -	clocks = <&k3_clks 61 0>;
> > -	clock-names = "gtc";
> > -};
> > -
> >  &cbass_main {
> >  	bootph-pre-ram;
> >  	sa3_secproxy: secproxy at 44880000 {
> > diff --git a/arch/arm/dts/k3-am642-r5-phycore-som-2gb.dts b/arch/arm/dts/k3-am642-r5-phycore-som-2gb.dts
> > index 4b7a63db4ce..6f3a2628353 100644
> > --- a/arch/arm/dts/k3-am642-r5-phycore-som-2gb.dts
> > +++ b/arch/arm/dts/k3-am642-r5-phycore-som-2gb.dts
> > @@ -21,8 +21,3 @@
> >  		ethernet0 = &cpsw3g;
> >  	};
> >  };
> > -
> > -&a53_0 {
> > -	clock-names = "gtc";
> > -	clocks = <&k3_clks 61 0>;
> > -};
>