[PATCH 1/7] clk: mediatek: rename HAVE_RST_BAR
David Lechner
dlechner at baylibre.com
Tue Feb 24 00:21:53 CET 2026
Rename HAVE_RST_BAR to CLK_PLL_HAVE_RST_BAR. This makes it more clear
that this flag only applies to PLL clocks. Also add a blank line between
CLK_PLL_HAVE_RST_BAR and the CLK_MUX_ macros to keep the grouping of the
flags consistent.
Signed-off-by: David Lechner <dlechner at baylibre.com>
---
drivers/clk/mediatek/clk-mt7622.c | 4 ++--
drivers/clk/mediatek/clk-mt7623.c | 4 ++--
drivers/clk/mediatek/clk-mt7629.c | 4 ++--
drivers/clk/mediatek/clk-mt8183.c | 12 ++++++------
drivers/clk/mediatek/clk-mt8188.c | 6 +++---
drivers/clk/mediatek/clk-mt8195.c | 6 +++---
drivers/clk/mediatek/clk-mt8365.c | 4 ++--
drivers/clk/mediatek/clk-mt8512.c | 4 ++--
drivers/clk/mediatek/clk-mt8516.c | 4 ++--
drivers/clk/mediatek/clk-mt8518.c | 4 ++--
drivers/clk/mediatek/clk-mtk.c | 4 ++--
drivers/clk/mediatek/clk-mtk.h | 3 ++-
12 files changed, 30 insertions(+), 29 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c
index 782eb14e9c5..108c0dcd14e 100644
--- a/drivers/clk/mediatek/clk-mt7622.c
+++ b/drivers/clk/mediatek/clk-mt7622.c
@@ -48,9 +48,9 @@
static const struct mtk_pll_data apmixed_plls[] = {
PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x1, 0,
21, 0x204, 24, 0x204, 0),
- PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0x1, HAVE_RST_BAR,
+ PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0x1, CLK_PLL_HAVE_RST_BAR,
21, 0x214, 24, 0x214, 0),
- PLL(CLK_APMIXED_UNIV2PLL, 0x220, 0x22c, 0x1, HAVE_RST_BAR,
+ PLL(CLK_APMIXED_UNIV2PLL, 0x220, 0x22c, 0x1, CLK_PLL_HAVE_RST_BAR,
7, 0x224, 24, 0x224, 14),
PLL(CLK_APMIXED_ETH1PLL, 0x300, 0x310, 0x1, 0,
21, 0x300, 1, 0x304, 0),
diff --git a/drivers/clk/mediatek/clk-mt7623.c b/drivers/clk/mediatek/clk-mt7623.c
index 071c4cf8a84..70570644ca4 100644
--- a/drivers/clk/mediatek/clk-mt7623.c
+++ b/drivers/clk/mediatek/clk-mt7623.c
@@ -61,9 +61,9 @@ static const int pll_id_offs_map[] = {
static const struct mtk_pll_data apmixed_plls[] = {
PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x80000001, 0,
21, 0x204, 24, 0x204, 0),
- PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0xf0000001, HAVE_RST_BAR,
+ PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0xf0000001, CLK_PLL_HAVE_RST_BAR,
21, 0x210, 4, 0x214, 0),
- PLL(CLK_APMIXED_UNIVPLL, 0x220, 0x22c, 0xf3000001, HAVE_RST_BAR,
+ PLL(CLK_APMIXED_UNIVPLL, 0x220, 0x22c, 0xf3000001, CLK_PLL_HAVE_RST_BAR,
7, 0x220, 4, 0x224, 14),
PLL(CLK_APMIXED_MMPLL, 0x230, 0x23c, 0x00000001, 0,
21, 0x230, 4, 0x234, 0),
diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-mt7629.c
index 582394f594b..7fe62bdcea5 100644
--- a/drivers/clk/mediatek/clk-mt7629.c
+++ b/drivers/clk/mediatek/clk-mt7629.c
@@ -48,9 +48,9 @@
static const struct mtk_pll_data apmixed_plls[] = {
PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x1, 0,
21, 0x204, 24, 0x204, 0),
- PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0x1, HAVE_RST_BAR,
+ PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0x1, CLK_PLL_HAVE_RST_BAR,
21, 0x214, 24, 0x214, 0),
- PLL(CLK_APMIXED_UNIV2PLL, 0x220, 0x22c, 0x1, HAVE_RST_BAR,
+ PLL(CLK_APMIXED_UNIV2PLL, 0x220, 0x22c, 0x1, CLK_PLL_HAVE_RST_BAR,
7, 0x224, 24, 0x224, 14),
PLL(CLK_APMIXED_ETH1PLL, 0x300, 0x310, 0x1, 0,
21, 0x300, 1, 0x304, 0),
diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c
index 9d9d00622db..752cb1c61ab 100644
--- a/drivers/clk/mediatek/clk-mt8183.c
+++ b/drivers/clk/mediatek/clk-mt8183.c
@@ -38,24 +38,24 @@
static const struct mtk_pll_data apmixed_plls[] = {
PLL(CLK_APMIXED_ARMPLL_LL, 0x0200, 0x020C, 0x00000001,
- HAVE_RST_BAR, BIT(24), 22, 8, 0x0204, 24,
+ CLK_PLL_HAVE_RST_BAR, BIT(24), 22, 8, 0x0204, 24,
0x0204, 0),
PLL(CLK_APMIXED_ARMPLL_L, 0x0210, 0x021C, 0x00000001,
- HAVE_RST_BAR, BIT(24), 22, 8, 0x0214, 24,
+ CLK_PLL_HAVE_RST_BAR, BIT(24), 22, 8, 0x0214, 24,
0x0214, 0),
PLL(CLK_APMIXED_CCIPLL, 0x0290, 0x029C, 0x00000001,
- HAVE_RST_BAR, BIT(24), 22, 8, 0x0294, 24,
+ CLK_PLL_HAVE_RST_BAR, BIT(24), 22, 8, 0x0294, 24,
0x0294, 0),
PLL(CLK_APMIXED_MAINPLL, 0x0220, 0x022C, 0x00000001,
- HAVE_RST_BAR, BIT(24), 22, 8, 0x0224, 24,
+ CLK_PLL_HAVE_RST_BAR, BIT(24), 22, 8, 0x0224, 24,
0x0224, 0),
PLL(CLK_APMIXED_UNIV2PLL, 0x0230, 0x023C, 0x00000001,
- HAVE_RST_BAR, BIT(24), 22, 8, 0x0234, 24,
+ CLK_PLL_HAVE_RST_BAR, BIT(24), 22, 8, 0x0234, 24,
0x0234, 0),
PLL(CLK_APMIXED_MSDCPLL, 0x0250, 0x025C, 0x00000001,
0, 0, 22, 8, 0x0254, 24, 0x0254, 0),
PLL(CLK_APMIXED_MMPLL, 0x0270, 0x027C, 0x00000001,
- HAVE_RST_BAR, BIT(23), 22, 8, 0x0274, 24,
+ CLK_PLL_HAVE_RST_BAR, BIT(23), 22, 8, 0x0274, 24,
0x0274, 0),
PLL(CLK_APMIXED_MFGPLL, 0x0240, 0x024C, 0x00000001,
0, 0, 22, 8, 0x0244, 24, 0x0244, 0),
diff --git a/drivers/clk/mediatek/clk-mt8188.c b/drivers/clk/mediatek/clk-mt8188.c
index b720eec8ba7..9d1da23d066 100644
--- a/drivers/clk/mediatek/clk-mt8188.c
+++ b/drivers/clk/mediatek/clk-mt8188.c
@@ -56,13 +56,13 @@ static const struct mtk_pll_data apmixed_plls[] = {
0x0528, 0),
PLL(CLK_APMIXED_TVDPLL2, 0x0534, 0x0540, 0, 0, 22, 0x0538, 24,
0x0538, 0),
- PLL(CLK_APMIXED_MMPLL, 0x0544, 0x0550, 0xff000000, HAVE_RST_BAR,
+ PLL(CLK_APMIXED_MMPLL, 0x0544, 0x0550, 0xff000000, CLK_PLL_HAVE_RST_BAR,
22, 0x0548, 24, 0x0548, 0),
- PLL(CLK_APMIXED_MAINPLL, 0x045C, 0x0468, 0xff000000, HAVE_RST_BAR,
+ PLL(CLK_APMIXED_MAINPLL, 0x045C, 0x0468, 0xff000000, CLK_PLL_HAVE_RST_BAR,
22, 0x0460, 24, 0x0460, 0),
PLL(CLK_APMIXED_IMGPLL, 0x0554, 0x0560, 0, 0, 22, 0x0558, 24,
0x0558, 0),
- PLL(CLK_APMIXED_UNIVPLL, 0x0504, 0x0510, 0xff000000, HAVE_RST_BAR,
+ PLL(CLK_APMIXED_UNIVPLL, 0x0504, 0x0510, 0xff000000, CLK_PLL_HAVE_RST_BAR,
22, 0x0508, 24, 0x0508, 0),
PLL(CLK_APMIXED_ADSPPLL, 0x042C, 0x0438, 0, 0, 22, 0x0430, 24,
0x0430, 0),
diff --git a/drivers/clk/mediatek/clk-mt8195.c b/drivers/clk/mediatek/clk-mt8195.c
index d05d56c9bf6..d9d63601cc4 100644
--- a/drivers/clk/mediatek/clk-mt8195.c
+++ b/drivers/clk/mediatek/clk-mt8195.c
@@ -62,15 +62,15 @@ static const struct mtk_pll_data apmixed_plls[] = {
0x00a8, 0, 0x00a8),
PLL(CLK_APMIXED_TVDPLL2, 0x00c0, 0x00d0, 0, 0, 0, 22, 0x00c8, 24,
0x00c8, 0, 0x00c8),
- PLL(CLK_APMIXED_MMPLL, 0x00e0, 0x00f0, 0xff000000, HAVE_RST_BAR,
+ PLL(CLK_APMIXED_MMPLL, 0x00e0, 0x00f0, 0xff000000, CLK_PLL_HAVE_RST_BAR,
BIT(23), 22, 0x00e8, 24, 0x00e8, 0, 0x00e8),
- PLL(CLK_APMIXED_MAINPLL, 0x01d0, 0x01e0, 0xff000000, HAVE_RST_BAR,
+ PLL(CLK_APMIXED_MAINPLL, 0x01d0, 0x01e0, 0xff000000, CLK_PLL_HAVE_RST_BAR,
BIT(23), 22, 0x01d8, 24, 0x01d8, 0, 0x01d8),
PLL(CLK_APMIXED_VDECPLL, 0x0890, 0x08a0, 0, 0, 0, 22, 0x0898, 24,
0x0898, 0, 0x0898),
PLL(CLK_APMIXED_IMGPLL, 0x0100, 0x0110, 0, 0, 0, 22, 0x0108, 24,
0x0108, 0, 0x0108),
- PLL(CLK_APMIXED_UNIVPLL, 0x01f0, 0x0700, 0xff000000, HAVE_RST_BAR,
+ PLL(CLK_APMIXED_UNIVPLL, 0x01f0, 0x0700, 0xff000000, CLK_PLL_HAVE_RST_BAR,
BIT(23), 22, 0x01f8, 24, 0x01f8, 0, 0x01f8),
PLL(CLK_APMIXED_HDMIPLL1, 0x08c0, 0x08d0, 0, 0, 0, 22, 0x08c8, 24,
0x08c8, 0, 0x08c8),
diff --git a/drivers/clk/mediatek/clk-mt8365.c b/drivers/clk/mediatek/clk-mt8365.c
index 6ba464097ae..2b1703e7203 100644
--- a/drivers/clk/mediatek/clk-mt8365.c
+++ b/drivers/clk/mediatek/clk-mt8365.c
@@ -45,9 +45,9 @@
static const struct mtk_pll_data apmixed_plls[] = {
PLL(CLK_APMIXED_ARMPLL, 0x030C, 0x0318, 0x00000001, PLL_AO, 22, 0x0310,
24, 0x0310, 0, 0, 0),
- PLL(CLK_APMIXED_MAINPLL, 0x0228, 0x0234, 0xFF000001, HAVE_RST_BAR, 22,
+ PLL(CLK_APMIXED_MAINPLL, 0x0228, 0x0234, 0xFF000001, CLK_PLL_HAVE_RST_BAR, 22,
0x022C, 24, 0x022C, 0, CON0_MT8365_RST_BAR, 0),
- PLL(CLK_APMIXED_UNIVPLL, 0x0208, 0x0214, 0xFF000001, HAVE_RST_BAR, 22,
+ PLL(CLK_APMIXED_UNIVPLL, 0x0208, 0x0214, 0xFF000001, CLK_PLL_HAVE_RST_BAR, 22,
0x020C, 24, 0x020C, 0, CON0_MT8365_RST_BAR, 0),
PLL(CLK_APMIXED_MFGPLL, 0x0218, 0x0224, 0x00000001, 0, 22, 0x021C, 24,
0x021C, 0, 0, 0),
diff --git a/drivers/clk/mediatek/clk-mt8512.c b/drivers/clk/mediatek/clk-mt8512.c
index e6ced91fd06..69576304f2f 100644
--- a/drivers/clk/mediatek/clk-mt8512.c
+++ b/drivers/clk/mediatek/clk-mt8512.c
@@ -41,9 +41,9 @@ static const struct mtk_pll_data apmixed_plls[] = {
PLL(CLK_APMIXED_ARMPLL, 0x030C, 0x0318, 0x00000001,
0, 22, 0x0310, 24, 0x0310, 0, 0),
PLL(CLK_APMIXED_MAINPLL, 0x0228, 0x0234, 0x00000001,
- HAVE_RST_BAR, 22, 0x022C, 24, 0x022C, 0, 0),
+ CLK_PLL_HAVE_RST_BAR, 22, 0x022C, 24, 0x022C, 0, 0),
PLL(CLK_APMIXED_UNIVPLL2, 0x0208, 0x0214, 0x00000001,
- HAVE_RST_BAR, 22, 0x020C, 24, 0x020C, 0, 0),
+ CLK_PLL_HAVE_RST_BAR, 22, 0x020C, 24, 0x020C, 0, 0),
PLL(CLK_APMIXED_MSDCPLL, 0x0350, 0x035C, 0x00000001,
0, 22, 0x0354, 24, 0x0354, 0, 0),
PLL(CLK_APMIXED_APLL1, 0x031C, 0x032C, 0x00000001,
diff --git a/drivers/clk/mediatek/clk-mt8516.c b/drivers/clk/mediatek/clk-mt8516.c
index 4985ba3e5ce..dac4aad61ef 100644
--- a/drivers/clk/mediatek/clk-mt8516.c
+++ b/drivers/clk/mediatek/clk-mt8516.c
@@ -37,9 +37,9 @@ static const struct mtk_pll_data apmixed_plls[] = {
PLL(CLK_APMIXED_ARMPLL, 0x0100, 0x0110, 0x00000001, 0,
21, 0x0104, 24, 0x0104, 0),
PLL(CLK_APMIXED_MAINPLL, 0x0120, 0x0130, 0x00000001,
- HAVE_RST_BAR, 21, 0x0124, 24, 0x0124, 0),
+ CLK_PLL_HAVE_RST_BAR, 21, 0x0124, 24, 0x0124, 0),
PLL(CLK_APMIXED_UNIVPLL, 0x0140, 0x0150, 0x30000001,
- HAVE_RST_BAR, 7, 0x0144, 24, 0x0144, 0),
+ CLK_PLL_HAVE_RST_BAR, 7, 0x0144, 24, 0x0144, 0),
PLL(CLK_APMIXED_MMPLL, 0x0160, 0x0170, 0x00000001, 0,
21, 0x0164, 24, 0x0164, 0),
PLL(CLK_APMIXED_APLL1, 0x0180, 0x0190, 0x00000001, 0,
diff --git a/drivers/clk/mediatek/clk-mt8518.c b/drivers/clk/mediatek/clk-mt8518.c
index 2fc492e7170..c19828def06 100644
--- a/drivers/clk/mediatek/clk-mt8518.c
+++ b/drivers/clk/mediatek/clk-mt8518.c
@@ -37,9 +37,9 @@ static const struct mtk_pll_data apmixed_plls[] = {
PLL(CLK_APMIXED_ARMPLL, 0x0100, 0x0110, 0x00000001,
0, 21, 0x0104, 24, 0x0104, 0),
PLL(CLK_APMIXED_MAINPLL, 0x0120, 0x0130, 0x00000001,
- HAVE_RST_BAR, 21, 0x0124, 24, 0x0124, 0),
+ CLK_PLL_HAVE_RST_BAR, 21, 0x0124, 24, 0x0124, 0),
PLL(CLK_APMIXED_UNIVPLL, 0x0140, 0x0150, 0x30000001,
- HAVE_RST_BAR, 7, 0x0144, 24, 0x0144, 0),
+ CLK_PLL_HAVE_RST_BAR, 7, 0x0144, 24, 0x0144, 0),
PLL(CLK_APMIXED_MMPLL, 0x0160, 0x0170, 0x00000001,
0, 21, 0x0164, 24, 0x0164, 0),
PLL(CLK_APMIXED_APLL1, 0x0180, 0x0190, 0x00000001,
diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
index 6f7e2144332..0f29627665b 100644
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -598,7 +598,7 @@ static int mtk_apmixedsys_enable(struct clk *clk)
udelay(20);
- if (pll->flags & HAVE_RST_BAR) {
+ if (pll->flags & CLK_PLL_HAVE_RST_BAR) {
r = readl(priv->base + pll->reg + REG_CON0);
r |= pll->rst_bar_mask;
writel(r, priv->base + pll->reg + REG_CON0);
@@ -622,7 +622,7 @@ static int mtk_apmixedsys_disable(struct clk *clk)
pll = &priv->tree->plls[clk->id];
- if (pll->flags & HAVE_RST_BAR) {
+ if (pll->flags & CLK_PLL_HAVE_RST_BAR) {
r = readl(priv->base + pll->reg + REG_CON0);
r &= ~pll->rst_bar_mask;
writel(r, priv->base + pll->reg + REG_CON0);
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index c4aeee49abd..806ec2ec20a 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -20,7 +20,8 @@
*/
#define CLK_BYPASS_XTAL BIT(0)
-#define HAVE_RST_BAR BIT(0)
+#define CLK_PLL_HAVE_RST_BAR BIT(0)
+
#define CLK_DOMAIN_SCPSYS BIT(0)
#define CLK_MUX_SETCLR_UPD BIT(1)
--
2.43.0
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