[PATCH 4/7] clk: mediatek: mt7622: change to struct mtk_parent
David Lechner
dlechner at baylibre.com
Tue Feb 24 00:21:56 CET 2026
Change mux parents to use struct mtk_parent instead of int. Since these
clocks have mixed parents, we should be using struct mtk_parent which
specifically handles this case.
Signed-off-by: David Lechner <dlechner at baylibre.com>
---
drivers/clk/mediatek/clk-mt7622.c | 330 +++++++++++++++++++-------------------
1 file changed, 167 insertions(+), 163 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c
index 77f3a9fc3d3..e420be5a137 100644
--- a/drivers/clk/mediatek/clk-mt7622.c
+++ b/drivers/clk/mediatek/clk-mt7622.c
@@ -159,231 +159,235 @@ static const struct mtk_fixed_factor top_fixed_divs[] = {
FACTOR0(CLK_TOP_ETH_500M, CLK_APMIXED_ETH1PLL, 1, 1),
};
-static const int axi_parents[] = {
- CLK_XTAL,
- CLK_TOP_SYSPLL1_D2,
- CLK_TOP_SYSPLL_D5,
- CLK_TOP_SYSPLL1_D4,
- CLK_TOP_UNIVPLL_D5,
- CLK_TOP_UNIVPLL2_D2,
- CLK_TOP_UNIVPLL_D7
+#define XTAL_PARENT(id) PARENT(id, CLK_PARENT_XTAL)
+#define TOP_PARENT(id) PARENT(id, CLK_PARENT_TOPCKGEN)
+#define VOID_PARENT PARENT(-1, 0)
+
+static const struct mtk_parent axi_parents[] = {
+ XTAL_PARENT(CLK_XTAL),
+ TOP_PARENT(CLK_TOP_SYSPLL1_D2),
+ TOP_PARENT(CLK_TOP_SYSPLL_D5),
+ TOP_PARENT(CLK_TOP_SYSPLL1_D4),
+ TOP_PARENT(CLK_TOP_UNIVPLL_D5),
+ TOP_PARENT(CLK_TOP_UNIVPLL2_D2),
+ TOP_PARENT(CLK_TOP_UNIVPLL_D7),
};
-static const int mem_parents[] = {
- CLK_XTAL,
- CLK_TOP_DMPLL
+static const struct mtk_parent mem_parents[] = {
+ XTAL_PARENT(CLK_XTAL),
+ TOP_PARENT(CLK_TOP_DMPLL),
};
-static const int ddrphycfg_parents[] = {
- CLK_XTAL,
- CLK_TOP_SYSPLL1_D8
+static const struct mtk_parent ddrphycfg_parents[] = {
+ XTAL_PARENT(CLK_XTAL),
+ TOP_PARENT(CLK_TOP_SYSPLL1_D8),
};
-static const int eth_parents[] = {
- CLK_XTAL,
- CLK_TOP_SYSPLL1_D2,
- CLK_TOP_UNIVPLL1_D2,
- CLK_TOP_SYSPLL1_D4,
- CLK_TOP_UNIVPLL_D5,
- -1,
- CLK_TOP_UNIVPLL_D7
+static const struct mtk_parent eth_parents[] = {
+ XTAL_PARENT(CLK_XTAL),
+ TOP_PARENT(CLK_TOP_SYSPLL1_D2),
+ TOP_PARENT(CLK_TOP_UNIVPLL1_D2),
+ TOP_PARENT(CLK_TOP_SYSPLL1_D4),
+ TOP_PARENT(CLK_TOP_UNIVPLL_D5),
+ VOID_PARENT,
+ TOP_PARENT(CLK_TOP_UNIVPLL_D7),
};
-static const int pwm_parents[] = {
- CLK_XTAL,
- CLK_TOP_UNIVPLL2_D4
+static const struct mtk_parent pwm_parents[] = {
+ XTAL_PARENT(CLK_XTAL),
+ TOP_PARENT(CLK_TOP_UNIVPLL2_D4),
};
-static const int f10m_ref_parents[] = {
- CLK_XTAL,
- CLK_TOP_SYSPLL4_D16
+static const struct mtk_parent f10m_ref_parents[] = {
+ XTAL_PARENT(CLK_XTAL),
+ TOP_PARENT(CLK_TOP_SYSPLL4_D16),
};
-static const int nfi_infra_parents[] = {
- CLK_XTAL,
- CLK_XTAL,
- CLK_XTAL,
- CLK_XTAL,
- CLK_XTAL,
- CLK_XTAL,
- CLK_XTAL,
- CLK_XTAL,
- CLK_TOP_UNIVPLL2_D8,
- CLK_TOP_SYSPLL1_D8,
- CLK_TOP_UNIVPLL1_D8,
- CLK_TOP_SYSPLL4_D2,
- CLK_TOP_UNIVPLL2_D4,
- CLK_TOP_UNIVPLL3_D2,
- CLK_TOP_SYSPLL1_D4
+static const struct mtk_parent nfi_infra_parents[] = {
+ XTAL_PARENT(CLK_XTAL),
+ XTAL_PARENT(CLK_XTAL),
+ XTAL_PARENT(CLK_XTAL),
+ XTAL_PARENT(CLK_XTAL),
+ XTAL_PARENT(CLK_XTAL),
+ XTAL_PARENT(CLK_XTAL),
+ XTAL_PARENT(CLK_XTAL),
+ XTAL_PARENT(CLK_XTAL),
+ TOP_PARENT(CLK_TOP_UNIVPLL2_D8),
+ TOP_PARENT(CLK_TOP_SYSPLL1_D8),
+ TOP_PARENT(CLK_TOP_UNIVPLL1_D8),
+ TOP_PARENT(CLK_TOP_SYSPLL4_D2),
+ TOP_PARENT(CLK_TOP_UNIVPLL2_D4),
+ TOP_PARENT(CLK_TOP_UNIVPLL3_D2),
+ TOP_PARENT(CLK_TOP_SYSPLL1_D4),
};
-static const int flash_parents[] = {
- CLK_XTAL,
- CLK_TOP_UNIVPLL_D80_D4,
- CLK_TOP_SYSPLL2_D8,
- CLK_TOP_SYSPLL3_D4,
- CLK_TOP_UNIVPLL3_D4,
- CLK_TOP_UNIVPLL1_D8,
- CLK_TOP_SYSPLL2_D4,
- CLK_TOP_UNIVPLL2_D4
+static const struct mtk_parent flash_parents[] = {
+ XTAL_PARENT(CLK_XTAL),
+ TOP_PARENT(CLK_TOP_UNIVPLL_D80_D4),
+ TOP_PARENT(CLK_TOP_SYSPLL2_D8),
+ TOP_PARENT(CLK_TOP_SYSPLL3_D4),
+ TOP_PARENT(CLK_TOP_UNIVPLL3_D4),
+ TOP_PARENT(CLK_TOP_UNIVPLL1_D8),
+ TOP_PARENT(CLK_TOP_SYSPLL2_D4),
+ TOP_PARENT(CLK_TOP_UNIVPLL2_D4),
};
-static const int uart_parents[] = {
- CLK_XTAL,
- CLK_TOP_UNIVPLL2_D8
+static const struct mtk_parent uart_parents[] = {
+ XTAL_PARENT(CLK_XTAL),
+ TOP_PARENT(CLK_TOP_UNIVPLL2_D8),
};
-static const int spi0_parents[] = {
- CLK_XTAL,
- CLK_TOP_SYSPLL3_D2,
- CLK_XTAL,
- CLK_TOP_SYSPLL2_D4,
- CLK_TOP_SYSPLL4_D2,
- CLK_TOP_UNIVPLL2_D4,
- CLK_TOP_UNIVPLL1_D8,
- CLK_XTAL
+static const struct mtk_parent spi0_parents[] = {
+ XTAL_PARENT(CLK_XTAL),
+ TOP_PARENT(CLK_TOP_SYSPLL3_D2),
+ XTAL_PARENT(CLK_XTAL),
+ TOP_PARENT(CLK_TOP_SYSPLL2_D4),
+ TOP_PARENT(CLK_TOP_SYSPLL4_D2),
+ TOP_PARENT(CLK_TOP_UNIVPLL2_D4),
+ TOP_PARENT(CLK_TOP_UNIVPLL1_D8),
+ XTAL_PARENT(CLK_XTAL),
};
-static const int spi1_parents[] = {
- CLK_XTAL,
- CLK_TOP_SYSPLL3_D2,
- CLK_XTAL,
- CLK_TOP_SYSPLL4_D4,
- CLK_TOP_SYSPLL4_D2,
- CLK_TOP_UNIVPLL2_D4,
- CLK_TOP_UNIVPLL1_D8,
- CLK_XTAL
+static const struct mtk_parent spi1_parents[] = {
+ XTAL_PARENT(CLK_XTAL),
+ TOP_PARENT(CLK_TOP_SYSPLL3_D2),
+ XTAL_PARENT(CLK_XTAL),
+ TOP_PARENT(CLK_TOP_SYSPLL4_D4),
+ TOP_PARENT(CLK_TOP_SYSPLL4_D2),
+ TOP_PARENT(CLK_TOP_UNIVPLL2_D4),
+ TOP_PARENT(CLK_TOP_UNIVPLL1_D8),
+ XTAL_PARENT(CLK_XTAL),
};
-static const int msdc30_0_parents[] = {
- CLK_XTAL,
- CLK_TOP_UNIVPLL2_D16,
- CLK_TOP_UNIV48M
+static const struct mtk_parent msdc30_0_parents[] = {
+ XTAL_PARENT(CLK_XTAL),
+ TOP_PARENT(CLK_TOP_UNIVPLL2_D16),
+ TOP_PARENT(CLK_TOP_UNIV48M),
};
-static const int a1sys_hp_parents[] = {
- CLK_XTAL,
- CLK_TOP_AUD1PLL,
- CLK_TOP_AUD2PLL,
- CLK_XTAL
+static const struct mtk_parent a1sys_hp_parents[] = {
+ XTAL_PARENT(CLK_XTAL),
+ TOP_PARENT(CLK_TOP_AUD1PLL),
+ TOP_PARENT(CLK_TOP_AUD2PLL),
+ XTAL_PARENT(CLK_XTAL),
};
-static const int intdir_parents[] = {
- CLK_XTAL,
- CLK_TOP_SYSPLL1_D2,
- CLK_TOP_UNIVPLL_D2,
- CLK_TOP_SGMIIPLL
+static const struct mtk_parent intdir_parents[] = {
+ XTAL_PARENT(CLK_XTAL),
+ TOP_PARENT(CLK_TOP_SYSPLL1_D2),
+ TOP_PARENT(CLK_TOP_UNIVPLL_D2),
+ TOP_PARENT(CLK_TOP_SGMIIPLL),
};
-static const int aud_intbus_parents[] = {
- CLK_XTAL,
- CLK_TOP_SYSPLL1_D4,
- CLK_TOP_SYSPLL4_D2,
- CLK_TOP_SYSPLL3_D2
+static const struct mtk_parent aud_intbus_parents[] = {
+ XTAL_PARENT(CLK_XTAL),
+ TOP_PARENT(CLK_TOP_SYSPLL1_D4),
+ TOP_PARENT(CLK_TOP_SYSPLL4_D2),
+ TOP_PARENT(CLK_TOP_SYSPLL3_D2),
};
-static const int pmicspi_parents[] = {
- CLK_XTAL,
- -1,
- -1,
- -1,
- -1,
- CLK_TOP_UNIVPLL2_D16
+static const struct mtk_parent pmicspi_parents[] = {
+ XTAL_PARENT(CLK_XTAL),
+ VOID_PARENT,
+ VOID_PARENT,
+ VOID_PARENT,
+ VOID_PARENT,
+ TOP_PARENT(CLK_TOP_UNIVPLL2_D16),
};
-static const int atb_parents[] = {
- CLK_XTAL,
- CLK_TOP_SYSPLL1_D2,
- CLK_TOP_SYSPLL_D5
+static const struct mtk_parent atb_parents[] = {
+ XTAL_PARENT(CLK_XTAL),
+ TOP_PARENT(CLK_TOP_SYSPLL1_D2),
+ TOP_PARENT(CLK_TOP_SYSPLL_D5),
};
-static const int audio_parents[] = {
- CLK_XTAL,
- CLK_TOP_SYSPLL3_D4,
- CLK_TOP_SYSPLL4_D4,
- CLK_TOP_UNIVPLL1_D16
+static const struct mtk_parent audio_parents[] = {
+ XTAL_PARENT(CLK_XTAL),
+ TOP_PARENT(CLK_TOP_SYSPLL3_D4),
+ TOP_PARENT(CLK_TOP_SYSPLL4_D4),
+ TOP_PARENT(CLK_TOP_UNIVPLL1_D16),
};
-static const int usb20_parents[] = {
- CLK_XTAL,
- CLK_TOP_UNIVPLL3_D4,
- CLK_TOP_SYSPLL1_D8,
- CLK_XTAL
+static const struct mtk_parent usb20_parents[] = {
+ XTAL_PARENT(CLK_XTAL),
+ TOP_PARENT(CLK_TOP_UNIVPLL3_D4),
+ TOP_PARENT(CLK_TOP_SYSPLL1_D8),
+ XTAL_PARENT(CLK_XTAL),
};
-static const int aud1_parents[] = {
- CLK_XTAL,
- CLK_TOP_AUD1PLL
+static const struct mtk_parent aud1_parents[] = {
+ XTAL_PARENT(CLK_XTAL),
+ TOP_PARENT(CLK_TOP_AUD1PLL),
};
-static const int asm_l_parents[] = {
- CLK_XTAL,
- CLK_TOP_SYSPLL_D5,
- CLK_TOP_UNIVPLL2_D2,
- CLK_TOP_UNIVPLL2_D4
+static const struct mtk_parent asm_l_parents[] = {
+ XTAL_PARENT(CLK_XTAL),
+ TOP_PARENT(CLK_TOP_SYSPLL_D5),
+ TOP_PARENT(CLK_TOP_UNIVPLL2_D2),
+ TOP_PARENT(CLK_TOP_UNIVPLL2_D4),
};
-static const int apll1_ck_parents[] = {
- CLK_TOP_AUD1_SEL,
- CLK_TOP_AUD2_SEL
+static const struct mtk_parent apll1_ck_parents[] = {
+ TOP_PARENT(CLK_TOP_AUD1_SEL),
+ TOP_PARENT(CLK_TOP_AUD2_SEL),
};
static const struct mtk_composite top_muxes[] = {
/* CLK_CFG_0 */
- MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7),
- MUX_GATE(CLK_TOP_MEM_SEL, mem_parents, 0x40, 8, 1, 15),
- MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x40, 16, 1, 23),
- MUX_GATE(CLK_TOP_ETH_SEL, eth_parents, 0x40, 24, 3, 31),
+ MUX_GATE_MIXED(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7),
+ MUX_GATE_MIXED(CLK_TOP_MEM_SEL, mem_parents, 0x40, 8, 1, 15),
+ MUX_GATE_MIXED(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x40, 16, 1, 23),
+ MUX_GATE_MIXED(CLK_TOP_ETH_SEL, eth_parents, 0x40, 24, 3, 31),
/* CLK_CFG_1 */
- MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7),
- MUX_GATE(CLK_TOP_F10M_REF_SEL, f10m_ref_parents, 0x50, 8, 1, 15),
- MUX_GATE(CLK_TOP_NFI_INFRA_SEL, nfi_infra_parents, 0x50, 16, 4, 23),
- MUX_GATE(CLK_TOP_FLASH_SEL, flash_parents, 0x50, 24, 3, 31),
+ MUX_GATE_MIXED(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7),
+ MUX_GATE_MIXED(CLK_TOP_F10M_REF_SEL, f10m_ref_parents, 0x50, 8, 1, 15),
+ MUX_GATE_MIXED(CLK_TOP_NFI_INFRA_SEL, nfi_infra_parents, 0x50, 16, 4, 23),
+ MUX_GATE_MIXED(CLK_TOP_FLASH_SEL, flash_parents, 0x50, 24, 3, 31),
/* CLK_CFG_2 */
- MUX_GATE(CLK_TOP_UART_SEL, uart_parents, 0x60, 0, 1, 7),
- MUX_GATE(CLK_TOP_SPI0_SEL, spi0_parents, 0x60, 8, 3, 15),
- MUX_GATE(CLK_TOP_SPI1_SEL, spi1_parents, 0x60, 16, 3, 23),
- MUX_GATE(CLK_TOP_MSDC50_0_SEL, uart_parents, 0x60, 24, 3, 31),
+ MUX_GATE_MIXED(CLK_TOP_UART_SEL, uart_parents, 0x60, 0, 1, 7),
+ MUX_GATE_MIXED(CLK_TOP_SPI0_SEL, spi0_parents, 0x60, 8, 3, 15),
+ MUX_GATE_MIXED(CLK_TOP_SPI1_SEL, spi1_parents, 0x60, 16, 3, 23),
+ MUX_GATE_MIXED(CLK_TOP_MSDC50_0_SEL, uart_parents, 0x60, 24, 3, 31),
/* CLK_CFG_3 */
- MUX_GATE(CLK_TOP_MSDC30_0_SEL, msdc30_0_parents, 0x70, 0, 3, 7),
- MUX_GATE(CLK_TOP_MSDC30_1_SEL, msdc30_0_parents, 0x70, 8, 3, 15),
- MUX_GATE(CLK_TOP_A1SYS_HP_SEL, a1sys_hp_parents, 0x70, 16, 3, 23),
- MUX_GATE(CLK_TOP_A2SYS_HP_SEL, a1sys_hp_parents, 0x70, 24, 3, 31),
+ MUX_GATE_MIXED(CLK_TOP_MSDC30_0_SEL, msdc30_0_parents, 0x70, 0, 3, 7),
+ MUX_GATE_MIXED(CLK_TOP_MSDC30_1_SEL, msdc30_0_parents, 0x70, 8, 3, 15),
+ MUX_GATE_MIXED(CLK_TOP_A1SYS_HP_SEL, a1sys_hp_parents, 0x70, 16, 3, 23),
+ MUX_GATE_MIXED(CLK_TOP_A2SYS_HP_SEL, a1sys_hp_parents, 0x70, 24, 3, 31),
/* CLK_CFG_4 */
- MUX_GATE(CLK_TOP_INTDIR_SEL, intdir_parents, 0x80, 0, 2, 7),
- MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x80, 8, 2, 15),
- MUX_GATE(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x80, 16, 3, 23),
- MUX_GATE(CLK_TOP_SCP_SEL, ddrphycfg_parents, 0x80, 24, 2, 31),
+ MUX_GATE_MIXED(CLK_TOP_INTDIR_SEL, intdir_parents, 0x80, 0, 2, 7),
+ MUX_GATE_MIXED(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x80, 8, 2, 15),
+ MUX_GATE_MIXED(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x80, 16, 3, 23),
+ MUX_GATE_MIXED(CLK_TOP_SCP_SEL, ddrphycfg_parents, 0x80, 24, 2, 31),
/* CLK_CFG_5 */
- MUX_GATE(CLK_TOP_ATB_SEL, atb_parents, 0x90, 0, 2, 7),
- MUX_GATE_FLAGS(CLK_TOP_HIF_SEL, eth_parents, 0x90, 8, 3, 15,
- CLK_MUX_DOMAIN_SCPSYS),
- MUX_GATE(CLK_TOP_AUDIO_SEL, audio_parents, 0x90, 16, 2, 23),
- MUX_GATE(CLK_TOP_U2_SEL, usb20_parents, 0x90, 24, 2, 31),
+ MUX_GATE_MIXED(CLK_TOP_ATB_SEL, atb_parents, 0x90, 0, 2, 7),
+ MUX_GATE_MIXED_FLAGS(CLK_TOP_HIF_SEL, eth_parents, 0x90, 8, 3, 15,
+ CLK_MUX_DOMAIN_SCPSYS),
+ MUX_GATE_MIXED(CLK_TOP_AUDIO_SEL, audio_parents, 0x90, 16, 2, 23),
+ MUX_GATE_MIXED(CLK_TOP_U2_SEL, usb20_parents, 0x90, 24, 2, 31),
/* CLK_CFG_6 */
- MUX_GATE(CLK_TOP_AUD1_SEL, aud1_parents, 0xA0, 0, 1, 7),
- MUX_GATE(CLK_TOP_AUD2_SEL, aud1_parents, 0xA0, 8, 1, 15),
- MUX_GATE(CLK_TOP_IRRX_SEL, f10m_ref_parents, 0xA0, 16, 1, 23),
- MUX_GATE(CLK_TOP_IRTX_SEL, f10m_ref_parents, 0xA0, 24, 1, 31),
+ MUX_GATE_MIXED(CLK_TOP_AUD1_SEL, aud1_parents, 0xA0, 0, 1, 7),
+ MUX_GATE_MIXED(CLK_TOP_AUD2_SEL, aud1_parents, 0xA0, 8, 1, 15),
+ MUX_GATE_MIXED(CLK_TOP_IRRX_SEL, f10m_ref_parents, 0xA0, 16, 1, 23),
+ MUX_GATE_MIXED(CLK_TOP_IRTX_SEL, f10m_ref_parents, 0xA0, 24, 1, 31),
/* CLK_CFG_7 */
- MUX_GATE(CLK_TOP_ASM_L_SEL, asm_l_parents, 0xB0, 0, 2, 7),
- MUX_GATE(CLK_TOP_ASM_M_SEL, asm_l_parents, 0xB0, 8, 2, 15),
- MUX_GATE(CLK_TOP_ASM_H_SEL, asm_l_parents, 0xB0, 16, 2, 23),
+ MUX_GATE_MIXED(CLK_TOP_ASM_L_SEL, asm_l_parents, 0xB0, 0, 2, 7),
+ MUX_GATE_MIXED(CLK_TOP_ASM_M_SEL, asm_l_parents, 0xB0, 8, 2, 15),
+ MUX_GATE_MIXED(CLK_TOP_ASM_H_SEL, asm_l_parents, 0xB0, 16, 2, 23),
/* CLK_AUDDIV_0 */
- MUX(CLK_TOP_APLL1_SEL, apll1_ck_parents, 0x120, 6, 1),
- MUX(CLK_TOP_APLL2_SEL, apll1_ck_parents, 0x120, 7, 1),
- MUX(CLK_TOP_I2S0_MCK_SEL, apll1_ck_parents, 0x120, 8, 1),
- MUX(CLK_TOP_I2S1_MCK_SEL, apll1_ck_parents, 0x120, 9, 1),
- MUX(CLK_TOP_I2S2_MCK_SEL, apll1_ck_parents, 0x120, 10, 1),
- MUX(CLK_TOP_I2S3_MCK_SEL, apll1_ck_parents, 0x120, 161, 1),
+ MUX_MIXED(CLK_TOP_APLL1_SEL, apll1_ck_parents, 0x120, 6, 1),
+ MUX_MIXED(CLK_TOP_APLL2_SEL, apll1_ck_parents, 0x120, 7, 1),
+ MUX_MIXED(CLK_TOP_I2S0_MCK_SEL, apll1_ck_parents, 0x120, 8, 1),
+ MUX_MIXED(CLK_TOP_I2S1_MCK_SEL, apll1_ck_parents, 0x120, 9, 1),
+ MUX_MIXED(CLK_TOP_I2S2_MCK_SEL, apll1_ck_parents, 0x120, 10, 1),
+ MUX_MIXED(CLK_TOP_I2S3_MCK_SEL, apll1_ck_parents, 0x120, 161, 1),
};
/* infracfg */
--
2.43.0
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