[PATCH 08/10] pinctrl: nxp: imx93: Support print pin muxing
Peng Fan (OSS)
peng.fan at oss.nxp.com
Wed Feb 25 02:29:34 CET 2026
From: Peng Fan <peng.fan at nxp.com>
Add support for printing pin names and current mux configuration on
i.MX93 when CMD_PINMUX is enabled.
- A full pin descriptor table for i.MX93 pads.
- Implementation of get_pins_count(), get_pin_name(), and
get_pin_muxing() in the i.MX9 pinctrl driver.
There is no good way to add real mux names, so just dump the function ID
from the mux register.
Signed-off-by: Peng Fan <peng.fan at nxp.com>
---
drivers/pinctrl/nxp/pinctrl-imx9.c | 49 ++++++++
drivers/pinctrl/nxp/pinctrl-imx93.c | 228 ++++++++++++++++++++++++++++++++++++
2 files changed, 277 insertions(+)
diff --git a/drivers/pinctrl/nxp/pinctrl-imx9.c b/drivers/pinctrl/nxp/pinctrl-imx9.c
index 39bcdeaa753..7e570c6b249 100644
--- a/drivers/pinctrl/nxp/pinctrl-imx9.c
+++ b/drivers/pinctrl/nxp/pinctrl-imx9.c
@@ -4,7 +4,11 @@
*/
#include <dm/device.h>
+#include <dm/device_compat.h>
#include <dm/pinctrl.h>
+#include <linux/bitops.h>
+#include <linux/types.h>
+#include <asm/io.h>
#include "pinctrl-imx.h"
@@ -18,7 +22,52 @@ static const struct udevice_id imx9_pinctrl_match[] = {
{ /* sentinel */ }
};
+#if CONFIG_IS_ENABLED(CMD_PINMUX)
+
+#if IS_ENABLED(CONFIG_IMX93)
+#include "pinctrl-imx93.c"
+#endif
+
+static int imx9_get_pins_count(struct udevice *dev)
+{
+ return ARRAY_SIZE(imx9_pinctrl_pads);
+}
+
+static const char *imx9_get_pin_name(struct udevice *dev, unsigned int selector)
+{
+ /* sanity checking */
+ if (selector != imx9_pinctrl_pads[selector].number) {
+ dev_err(dev,
+ "selector(%u) not match with imx9_pinctrl_pads[selector].number(%u)\n",
+ selector, imx9_pinctrl_pads[selector].number);
+ return NULL;
+ }
+
+ return imx9_pinctrl_pads[selector].name;
+}
+
+static int imx9_get_pin_muxing(struct udevice *dev, unsigned int selector,
+ char *buf, int size)
+{
+ struct imx_pinctrl_priv *priv = dev_get_priv(dev);
+ struct imx_pinctrl_soc_info *info = priv->info;
+ u32 mux_reg = selector << 2;
+ u32 mux_mode = readl(info->base + mux_reg);
+ u32 sion = mux_mode >> 4;
+
+ snprintf(buf, size, "Function(%d) SION(%d) at: 0x%p", mux_mode & 0x7, sion,
+ info->base + mux_reg);
+
+ return 0;
+}
+#endif
+
static const struct pinctrl_ops imx9_pinctrl_ops = {
+#if CONFIG_IS_ENABLED(CMD_PINMUX)
+ .get_pin_name = imx9_get_pin_name,
+ .get_pins_count = imx9_get_pins_count,
+ .get_pin_muxing = imx9_get_pin_muxing,
+#endif
.set_state = imx_pinctrl_set_state_mmio,
};
diff --git a/drivers/pinctrl/nxp/pinctrl-imx93.c b/drivers/pinctrl/nxp/pinctrl-imx93.c
new file mode 100644
index 00000000000..d13969856f6
--- /dev/null
+++ b/drivers/pinctrl/nxp/pinctrl-imx93.c
@@ -0,0 +1,228 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2026 NXP
+ */
+
+#include "pinctrl-imx.h"
+
+enum imx93_pads {
+ DAP_TDI = 0,
+ DAP_TMS_SWDIO = 1,
+ DAP_TCLK_SWCLK = 2,
+ DAP_TDO_TRACESWO = 3,
+ GPIO_IO00 = 4,
+ GPIO_IO01 = 5,
+ GPIO_IO02 = 6,
+ GPIO_IO03 = 7,
+ GPIO_IO04 = 8,
+ GPIO_IO05 = 9,
+ GPIO_IO06 = 10,
+ GPIO_IO07 = 11,
+ GPIO_IO08 = 12,
+ GPIO_IO09 = 13,
+ GPIO_IO10 = 14,
+ GPIO_IO11 = 15,
+ GPIO_IO12 = 16,
+ GPIO_IO13 = 17,
+ GPIO_IO14 = 18,
+ GPIO_IO15 = 19,
+ GPIO_IO16 = 20,
+ GPIO_IO17 = 21,
+ GPIO_IO18 = 22,
+ GPIO_IO19 = 23,
+ GPIO_IO20 = 24,
+ GPIO_IO21 = 25,
+ GPIO_IO22 = 26,
+ GPIO_IO23 = 27,
+ GPIO_IO24 = 28,
+ GPIO_IO25 = 29,
+ GPIO_IO26 = 30,
+ GPIO_IO27 = 31,
+ GPIO_IO28 = 32,
+ GPIO_IO29 = 33,
+ CCM_CLKO1 = 34,
+ CCM_CLKO2 = 35,
+ CCM_CLKO3 = 36,
+ CCM_CLKO4 = 37,
+ ENET1_MDC = 38,
+ ENET1_MDIO = 39,
+ ENET1_TD3 = 40,
+ ENET1_TD2 = 41,
+ ENET1_TD1 = 42,
+ ENET1_TD0 = 43,
+ ENET1_TX_CTL = 44,
+ ENET1_TXC = 45,
+ ENET1_RX_CTL = 46,
+ ENET1_RXC = 47,
+ ENET1_RD0 = 48,
+ ENET1_RD1 = 49,
+ ENET1_RD2 = 50,
+ ENET1_RD3 = 51,
+ ENET2_MDC = 52,
+ ENET2_MDIO = 53,
+ ENET2_TD3 = 54,
+ ENET2_TD2 = 55,
+ ENET2_TD1 = 56,
+ ENET2_TD0 = 57,
+ ENET2_TX_CTL = 58,
+ ENET2_TXC = 59,
+ ENET2_RX_CTL = 60,
+ ENET2_RXC = 61,
+ ENET2_RD0 = 62,
+ ENET2_RD1 = 63,
+ ENET2_RD2 = 64,
+ ENET2_RD3 = 65,
+ SD1_CLK = 66,
+ SD1_CMD = 67,
+ SD1_DATA0 = 68,
+ SD1_DATA1 = 69,
+ SD1_DATA2 = 70,
+ SD1_DATA3 = 71,
+ SD1_DATA4 = 72,
+ SD1_DATA5 = 73,
+ SD1_DATA6 = 74,
+ SD1_DATA7 = 75,
+ SD1_STROBE = 76,
+ SD2_VSELECT = 77,
+ SD3_CLK = 78,
+ SD3_CMD = 79,
+ SD3_DATA0 = 80,
+ SD3_DATA1 = 81,
+ SD3_DATA2 = 82,
+ SD3_DATA3 = 83,
+ SD2_CD_B = 84,
+ SD2_CLK = 85,
+ SD2_CMD = 86,
+ SD2_DATA0 = 87,
+ SD2_DATA1 = 88,
+ SD2_DATA2 = 89,
+ SD2_DATA3 = 90,
+ SD2_RESET_B = 91,
+ I2C1_SCL = 92,
+ I2C1_SDA = 93,
+ I2C2_SCL = 94,
+ I2C2_SDA = 95,
+ UART1_RXD = 96,
+ UART1_TXD = 97,
+ UART2_RXD = 98,
+ UART2_TXD = 99,
+ PDM_CLK = 100,
+ PDM_BIT_STREAM0 = 101,
+ PDM_BIT_STREAM1 = 102,
+ SAI1_TXFS = 103,
+ SAI1_TXC = 104,
+ SAI1_TXD0 = 105,
+ SAI1_RXD0 = 106,
+ WDOG_ANY = 107,
+};
+
+static const struct imx_pinctrl_pin_desc imx9_pinctrl_pads[] = {
+ IMX_PINCTRL_PIN(DAP_TDI),
+ IMX_PINCTRL_PIN(DAP_TMS_SWDIO),
+ IMX_PINCTRL_PIN(DAP_TCLK_SWCLK),
+ IMX_PINCTRL_PIN(DAP_TDO_TRACESWO),
+ IMX_PINCTRL_PIN(GPIO_IO00),
+ IMX_PINCTRL_PIN(GPIO_IO01),
+ IMX_PINCTRL_PIN(GPIO_IO02),
+ IMX_PINCTRL_PIN(GPIO_IO03),
+ IMX_PINCTRL_PIN(GPIO_IO04),
+ IMX_PINCTRL_PIN(GPIO_IO05),
+ IMX_PINCTRL_PIN(GPIO_IO06),
+ IMX_PINCTRL_PIN(GPIO_IO07),
+ IMX_PINCTRL_PIN(GPIO_IO08),
+ IMX_PINCTRL_PIN(GPIO_IO09),
+ IMX_PINCTRL_PIN(GPIO_IO10),
+ IMX_PINCTRL_PIN(GPIO_IO11),
+ IMX_PINCTRL_PIN(GPIO_IO12),
+ IMX_PINCTRL_PIN(GPIO_IO13),
+ IMX_PINCTRL_PIN(GPIO_IO14),
+ IMX_PINCTRL_PIN(GPIO_IO15),
+ IMX_PINCTRL_PIN(GPIO_IO16),
+ IMX_PINCTRL_PIN(GPIO_IO17),
+ IMX_PINCTRL_PIN(GPIO_IO18),
+ IMX_PINCTRL_PIN(GPIO_IO19),
+ IMX_PINCTRL_PIN(GPIO_IO20),
+ IMX_PINCTRL_PIN(GPIO_IO21),
+ IMX_PINCTRL_PIN(GPIO_IO22),
+ IMX_PINCTRL_PIN(GPIO_IO23),
+ IMX_PINCTRL_PIN(GPIO_IO24),
+ IMX_PINCTRL_PIN(GPIO_IO25),
+ IMX_PINCTRL_PIN(GPIO_IO26),
+ IMX_PINCTRL_PIN(GPIO_IO27),
+ IMX_PINCTRL_PIN(GPIO_IO28),
+ IMX_PINCTRL_PIN(GPIO_IO29),
+ IMX_PINCTRL_PIN(CCM_CLKO1),
+ IMX_PINCTRL_PIN(CCM_CLKO2),
+ IMX_PINCTRL_PIN(CCM_CLKO3),
+ IMX_PINCTRL_PIN(CCM_CLKO4),
+ IMX_PINCTRL_PIN(ENET1_MDC),
+ IMX_PINCTRL_PIN(ENET1_MDIO),
+ IMX_PINCTRL_PIN(ENET1_TD3),
+ IMX_PINCTRL_PIN(ENET1_TD2),
+ IMX_PINCTRL_PIN(ENET1_TD1),
+ IMX_PINCTRL_PIN(ENET1_TD0),
+ IMX_PINCTRL_PIN(ENET1_TX_CTL),
+ IMX_PINCTRL_PIN(ENET1_TXC),
+ IMX_PINCTRL_PIN(ENET1_RX_CTL),
+ IMX_PINCTRL_PIN(ENET1_RXC),
+ IMX_PINCTRL_PIN(ENET1_RD0),
+ IMX_PINCTRL_PIN(ENET1_RD1),
+ IMX_PINCTRL_PIN(ENET1_RD2),
+ IMX_PINCTRL_PIN(ENET1_RD3),
+ IMX_PINCTRL_PIN(ENET2_MDC),
+ IMX_PINCTRL_PIN(ENET2_MDIO),
+ IMX_PINCTRL_PIN(ENET2_TD3),
+ IMX_PINCTRL_PIN(ENET2_TD2),
+ IMX_PINCTRL_PIN(ENET2_TD1),
+ IMX_PINCTRL_PIN(ENET2_TD0),
+ IMX_PINCTRL_PIN(ENET2_TX_CTL),
+ IMX_PINCTRL_PIN(ENET2_TXC),
+ IMX_PINCTRL_PIN(ENET2_RX_CTL),
+ IMX_PINCTRL_PIN(ENET2_RXC),
+ IMX_PINCTRL_PIN(ENET2_RD0),
+ IMX_PINCTRL_PIN(ENET2_RD1),
+ IMX_PINCTRL_PIN(ENET2_RD2),
+ IMX_PINCTRL_PIN(ENET2_RD3),
+ IMX_PINCTRL_PIN(SD1_CLK),
+ IMX_PINCTRL_PIN(SD1_CMD),
+ IMX_PINCTRL_PIN(SD1_DATA0),
+ IMX_PINCTRL_PIN(SD1_DATA1),
+ IMX_PINCTRL_PIN(SD1_DATA2),
+ IMX_PINCTRL_PIN(SD1_DATA3),
+ IMX_PINCTRL_PIN(SD1_DATA4),
+ IMX_PINCTRL_PIN(SD1_DATA5),
+ IMX_PINCTRL_PIN(SD1_DATA6),
+ IMX_PINCTRL_PIN(SD1_DATA7),
+ IMX_PINCTRL_PIN(SD1_STROBE),
+ IMX_PINCTRL_PIN(SD2_VSELECT),
+ IMX_PINCTRL_PIN(SD3_CLK),
+ IMX_PINCTRL_PIN(SD3_CMD),
+ IMX_PINCTRL_PIN(SD3_DATA0),
+ IMX_PINCTRL_PIN(SD3_DATA1),
+ IMX_PINCTRL_PIN(SD3_DATA2),
+ IMX_PINCTRL_PIN(SD3_DATA3),
+ IMX_PINCTRL_PIN(SD2_CD_B),
+ IMX_PINCTRL_PIN(SD2_CLK),
+ IMX_PINCTRL_PIN(SD2_CMD),
+ IMX_PINCTRL_PIN(SD2_DATA0),
+ IMX_PINCTRL_PIN(SD2_DATA1),
+ IMX_PINCTRL_PIN(SD2_DATA2),
+ IMX_PINCTRL_PIN(SD2_DATA3),
+ IMX_PINCTRL_PIN(SD2_RESET_B),
+ IMX_PINCTRL_PIN(I2C1_SCL),
+ IMX_PINCTRL_PIN(I2C1_SDA),
+ IMX_PINCTRL_PIN(I2C2_SCL),
+ IMX_PINCTRL_PIN(I2C2_SDA),
+ IMX_PINCTRL_PIN(UART1_RXD),
+ IMX_PINCTRL_PIN(UART1_TXD),
+ IMX_PINCTRL_PIN(UART2_RXD),
+ IMX_PINCTRL_PIN(UART2_TXD),
+ IMX_PINCTRL_PIN(PDM_CLK),
+ IMX_PINCTRL_PIN(PDM_BIT_STREAM0),
+ IMX_PINCTRL_PIN(PDM_BIT_STREAM1),
+ IMX_PINCTRL_PIN(SAI1_TXFS),
+ IMX_PINCTRL_PIN(SAI1_TXC),
+ IMX_PINCTRL_PIN(SAI1_TXD0),
+ IMX_PINCTRL_PIN(SAI1_RXD0),
+ IMX_PINCTRL_PIN(WDOG_ANY),
+};
--
2.51.0
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