[PATCH 1/1] riscv: mpfs: SIFIVE_CLINT and SPL_SIFIVE_CLINT don't exist

[Heinrich Schuchardt]

On 2/25/26 11:40, Conor Dooley wrote:
> On Wed, Feb 25, 2026 at 11:28:31AM +0100, Heinrich Schuchardt wrote:
>> Don't imply non-existent symbols CONFIG_SIFIVE_CLINT and SPL_SIFIVE_CLINT.
>>
>> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>
>> ---
>>   arch/riscv/cpu/mpfs/Kconfig | 2 --
>>   1 file changed, 2 deletions(-)
>>
>> diff --git a/arch/riscv/cpu/mpfs/Kconfig b/arch/riscv/cpu/mpfs/Kconfig
>> index bcf1ede818b..8054313d182 100644
>> --- a/arch/riscv/cpu/mpfs/Kconfig
>> +++ b/arch/riscv/cpu/mpfs/Kconfig
>> @@ -6,8 +6,6 @@ config MICROCHIP_MPFS
>>   	imply CPU
>>   	imply CPU_RISCV
>>   	imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
>> -	imply SIFIVE_CLINT if RISCV_MMODE
>> -	imply SPL_SIFIVE_CLINT if SPL_RISCV_MMODE
> 
> Is this correct? Does it not mean that I just didn't update these to
> match the rename done in 9675d920278 ("riscv: Rename SiFive CLINT to
> RISC-V ALINT")? My original patch I think predates that rename, so I
> probably just sent it on without testing these since we don't use SPL
> or U-Boot in M-Mode. If the generic CPU wants them in these scenarios,
> then we do too, so the renamed versions are probably a better fit?
> 
>>   	imply CMD_CPU
>>   	imply SPL_CPU
>>   	imply SPL_OPENSBI
>> -- 
>> 2.51.0
>>

MPFS boards neither use SPL nor do they run main U-Boot in M-mode.
(SPL_)ACLINT seems irrelevant here.

Best regards

Heinrich