[v2 PATCH] mach-k3: Defer CTRL_MMR access until after TIFS version response

[Tom Rini]

On Thu, Feb 26, 2026 at 10:20:11AM +0530, Kumar, Udit wrote:
> 
> 
> On 2/26/2026 10:04 AM, Vignesh Raghavendra wrote:
> > 
> > 
> > On 25/02/26 10:45, Udit Kumar wrote:
> >> The CTRL_MMR registers are firewalled at boot time, and TIFS unlock
> >> them as part of the system firmware initialization sequence.
> >>
> >> Current code assumes the CTRL_MMR space can be accessible at early
> >> stage of board_init_f execution by unlocking them.
> >>
> >> But on HS-SE devices, TIFS takes more time to complete initialization,
> >> and CTRL_MMR registers remains firewalled and not getting unlocked.
> >> Which results in any write to these registers are ignored.
> > 
> > Hmm, this looks like something that can happen on other K3 SoCs too.
> > Should we update all the other SoCs to follow the same logic?
> 
> Yes, we need to update all SOCs,
> As Bryan pointed out, this issue is seen on other SOC as well[0].
> 
> I will post for other SOCs as different series. 

Do you mean another iteration of this, as a series that addresses all of
the SoCs? I'd prefer that (and cover letter explaining the situation) if
possible and reasonable, thanks.

-- 
Tom
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