[PATCH v1] arm: socfpga: Gen5/A10: Enable Designware watchdog

[Boon Khai Ng]

From: Tien Fong Chee <tien.fong.chee at altera.com>

Some bootROMs enable the watchdog before jumping to SPL, so calling
WATCHDOG_RESET() is required to reset watchdog timely especially
in long looping. Enable Designware watchdog driver is required to
support WATCHDOG_RESET().

Gen5 uses non device model watchdog HW_WATCHDOG due to OCRAM size
limitation.

Signed-off-by: Tien Fong Chee <tien.fong.chee at altera.com>
Signed-off-by: Boon Khai Ng <boon.khai.ng at altera.com>
---
 arch/arm/mach-socfpga/Kconfig | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index aec0fb7b1c8..49920a8a4d5 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -90,8 +90,10 @@ config ARCH_SOCFPGA_ARRIA10
 	select SPL_ALTERA_SDRAM
 	select SPL_BOARD_INIT if SPL
 	select SPL_CACHE if SPL
+	select SPL_WDT if SPL
 	select CLK
 	select SPL_CLK if SPL
+	select DESIGNWARE_WATCHDOG
 	select DM_I2C
 	select DM_RESET
 	select SPL_DM_RESET if SPL
@@ -100,6 +102,7 @@ config ARCH_SOCFPGA_ARRIA10
 	select SYSCON
 	select SPL_SYSCON if SPL
 	select ETH_DESIGNWARE_SOCFPGA
+	select WDT
 	imply FPGA_SOCFPGA
 	imply SPL_USE_TINY_PRINTF
 
@@ -117,6 +120,7 @@ config ARCH_SOCFPGA_CYCLONE5
 
 config ARCH_SOCFPGA_GEN5
 	bool
+	select DESIGNWARE_WATCHDOG
 	select SPL_ALTERA_SDRAM
 	imply FPGA_SOCFPGA
 	imply SPL_SIZE_LIMIT_SUBTRACT_GD
-- 
2.43.7