[PATCH v3 3/3] clk: stm32: Update clock management for STM32MP13/25

[Marek Vasut]

On 1/5/26 3:30 PM, Patrice CHOTARD wrote:

Hello Patrice,

>>>>>        /* WWDG */
>>>>> -    STM32_GATE(CK_BUS_WWDG1, "ck_icn_p_wwdg1", "ck_icn_apb3", 0, GATE_WWDG1,
>>>>> +    STM32_GATE(CK_BUS_WWDG1, "ck_icn_p_wwdg1", IDX_ICN_APB3, 0, GATE_WWDG1,
>>>>>               SEC_RIFSC(103)),
>>>>> -    STM32_GATE(CK_BUS_WWDG2, "ck_icn_p_wwdg2", "ck_icn_ls_mcu", 0, GATE_WWDG2,
>>>>> +    STM32_GATE(CK_BUS_WWDG2, "ck_icn_p_wwdg2", IDX_ICN_LS_MCU, 0, GATE_WWDG2,
>>>>>               SEC_RIFSC(104)),
>>>>>    };
>>>>>   
>>>> Hi Marek
>>>>
>>>> Can you give this patchset a try on DHCOR board in SPL ?
>>> I have bad news, the SPL does not even start with this, no output on UART even. The problem seems to be in 3/3 , if I apply only 1/3 and 2/3 the board does boot just fine.
> 
> Hi Marek
> 
> Happy new year ;-)

Thank you, Happy New Year to you too.

> Have you tried with DEBUG_UART ?

No, that is not enabled in the DHSBC config.

You should be able to try the SPL on MP13 EV if you pick the changes 
from these three commits (a few DT changes and a few config options), it 
should be straightforward to port over and help you debug the problem:

bf53344bff8d ("ARM: dts: stm32: Add STM32MP13x SPL specific DT additions")
1143fd4c3507 ("ARM: dts: stm32: Add SPL specifics for DH STM32MP13xx 
DHCOR DHSBC")
998da69da678 ("ARM: dts: stm32: Switch defconfig to SPL for DH 
STM32MP13xx DHCOR DHSBC")

If this doesn't work quickly for you, I can try to set up the MP13 DHSBC 
with DEBUG_UART later this week.