[PATCH] PCI: Add power sequencing driver for PCI slots

[Sean Anderson]

Extend the PCI bridge driver to enable resources associated with PCI
slots like clocks, power rails, and resets. This is modeled off of the
PCI power control subsystem in Linux. The traditional compatible for PCI
slots in U-Boot is pci-bridge, but Linux uses the more-systematic
pciclass,0604 so add that as an option.

Signed-off-by: Sean Anderson <sean.anderson at linux.dev>
---

 drivers/pci/Kconfig      |  8 ++++++
 drivers/pci/pci-uclass.c | 55 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 63 insertions(+)

diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index ea9868425d0..efac18b33f6 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -100,6 +100,14 @@ config PCI_ENHANCED_ALLOCATION
 	  Enable support for Enhanced Allocation which can be used by supported
 	  devices in place of traditional BARS for allocation of resources.
 
+config PCI_PWRCTRL_SLOT
+	bool "PCI slot power control"
+	help
+	  This is a generic driver that controls the power state of different
+	  PCI slots. The clocks and resets for the PCI slots are expected to be
+	  defined in the devicetree node of the PCI bridge. Say N if your PCI
+	  busses don't have software-controlled clocks or power rails.
+
 config PCI_ARID
         bool "Enable Alternate Routing-ID support for PCI"
         help
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index c370f8c6400..c5b1ddec45a 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -6,6 +6,7 @@
 
 #define LOG_CATEGORY UCLASS_PCI
 
+#include <clk.h>
 #include <dm.h>
 #include <errno.h>
 #include <init.h>
@@ -14,6 +15,7 @@
 #include <pci.h>
 #include <spl.h>
 #include <asm/global_data.h>
+#include <asm/gpio.h>
 #include <asm/io.h>
 #include <dm/device-internal.h>
 #include <dm/lists.h>
@@ -1893,13 +1895,66 @@ static const struct dm_pci_ops pci_bridge_ops = {
 
 static const struct udevice_id pci_bridge_ids[] = {
 	{ .compatible = "pci-bridge" },
+	{ .compatible = "pciclass,0604" },
 	{ }
 };
 
+static int __maybe_unused pci_bridge_probe(struct udevice *dev)
+{
+	struct clk clk;
+	struct gpio_desc perst;
+
+	if (!clk_get_by_index(dev, 0, &clk)) {
+		int ret = clk_enable(&clk);
+
+		if (ret)
+			return log_msg_ret("clk", ret);
+
+		/* Delay for T_PERST-CLK (100 us for all slot types) */
+		udelay(100);
+	}
+
+	if (!gpio_request_by_name(dev, "reset-gpios", 0, &perst, 0)) {
+		unsigned long delay = 0;
+		int ret;
+
+		/*
+		 * If PERST is inactive, the following call to dm_gpio_clrset_flags
+		 * will be the first time we assert it and we will need to
+		 * delay for T_PERST.
+		 */
+		if (dm_gpio_get_value(&perst) != 1)
+			delay = 100;
+
+		ret = dm_gpio_clrset_flags(&perst, GPIOD_MASK_DIR,
+					   GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+		if (ret)
+			return log_msg_ret("set", ret);
+		mdelay(delay);
+
+		ret = dm_gpio_set_value(&perst, 0);
+		if (ret)
+			return log_msg_ret("clr", ret);
+
+		/*
+		 * PCIe section 6.6.1:
+		 * > ... software must wait a minimum of 100 ms before sending a
+		 * > Configuration Request to the device immediately below that
+		 * > Port.
+		 */
+		mdelay(100);
+	}
+
+	return 0;
+}
+
 U_BOOT_DRIVER(pci_bridge_drv) = {
 	.name		= "pci_bridge_drv",
 	.id		= UCLASS_PCI,
 	.of_match	= pci_bridge_ids,
+#if CONFIG_IS_ENABLED(PCI_PWRCTRL_SLOT)
+	.probe		= pci_bridge_probe,
+#endif
 	.ops		= &pci_bridge_ops,
 };
 
-- 
2.35.1.1320.gc452695387.dirty

base-commit: 38ace442b630c5ddf049af83e8db229c012ed355
branch: pci_pwrseq