RV1103B: Attempt to upstream

[Quentin Schulz]

Hi Fabio,

On 12/19/25 3:45 AM, Fabio Estevam wrote:
> Hi,
> 
> I have a custom board based on the Rockchip evb-rv1103 (RV1103B silicon),
> booting from SPI-NAND.
> 
> I can successfully boot the vendor Rockchip U-Boot v2017.09 on this board,
> from SPI-NAND
> 
> I am currently working on upstreaming U-Boot support for the RV1103B SoC.
> My first RFC attempt is available here:
> 
>    https://github.com/fabioestevam/u-boot/commits/rv1103/
> 
> Build steps:
> 
>    make evb-rv1103_defconfig
>    make
> 
> However, I am not yet able to boot U-Boot on the board. At the moment,
> the board does not boot and only prints "RKUART".
> 
> My initial plan was to avoid SPL, similar to the evb-rv1108 approach
> (described in board/rockchip/evb_rv1108/README).
> 

There is an SPL, it's just a blob from Rockchip.

> Before going further, I would like to ask:
> 
> Is the evb-rv1108 “no SPL” boot flow a valid reference for RV1103B?
> 

No clue.

> Any guidance or pointers would be greatly appreciated.
> 

Do you actually use the same SPL blob as in the v2017.09 image? Do you 
see something on UART on that image?

I would think the SPL blob from Rockchip would print a bunch of things 
on the UART (e.g. while initializing the DDR like it's used to on 
RK3588). If you are using a different baudrate than the one set in the 
blob (usually 1500000 but maybe it's different for RV?), serial 
controller or serial IO mux (the number after M in the pinmux, e.g. 
UARTXMY means controller X mux Y), you can modify it with 
https://github.com/rockchip-linux/rkbin/blob/master/tools/ddrbin_tool.py.

RV1103 is somewhat old, but I'm assuming it's not impacted by the bug 
that requires us to use rkspi (instead of rksd) format for SPI images? 
You would need to write 2KiB every 4KiB IIRC. You can check after 
flashing the downstream image what is the content of your flash I guess 
to check that.

Usually, the blobs from Rockchip end up returning to BootROM for the 
next stage, so U-Boot proper would need to be stored somewhere in DRAM 
and jumping to it by the BootROM for it to work? Not sure about those 
details, I have been fortunate enough so far that I didn't have to do 
any SoC bring-up but maybe Jonas or Kever can help here?

Good luck!
Quentin