[PATCH 06/17] dts: k1: import dts file from upstream folder
Raymond Mao
raymondmaoca at gmail.com
Sat Jan 17 20:01:40 CET 2026
From: Raymond Mao <raymond.mao at riscstar.com>
Import K1.dtsi from upstream folder.
Signed-off-by: Raymond Mao <raymond.mao at riscstar.com>
---
arch/riscv/dts/k1.dtsi | 562 +++++++++++++++++++++++++++++++++--------
1 file changed, 460 insertions(+), 102 deletions(-)
diff --git a/arch/riscv/dts/k1.dtsi b/arch/riscv/dts/k1.dtsi
index 9c203eb4b79..20f1cb57462 100644
--- a/arch/riscv/dts/k1.dtsi
+++ b/arch/riscv/dts/k1.dtsi
@@ -1,8 +1,11 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright (C) 2024 Yangyu Chen <cyy at cyyself.name>
*/
+#include <dt-bindings/clock/spacemit,k1-syscon.h>
+#include <dt-bindings/reset/spacemit-k1-reset.h>
+
/dts-v1/;
/ {
#address-cells = <2>;
@@ -10,18 +13,6 @@
model = "SpacemiT K1";
compatible = "spacemit,k1";
- aliases {
- serial0 = &uart0;
- serial1 = &uart2;
- serial2 = &uart3;
- serial3 = &uart4;
- serial4 = &uart5;
- serial5 = &uart6;
- serial6 = &uart7;
- serial7 = &uart8;
- serial8 = &uart9;
- };
-
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -318,6 +309,36 @@
};
};
+ clocks {
+ vctcxo_1m: clock-1m {
+ compatible = "fixed-clock";
+ clock-frequency = <1000000>;
+ clock-output-names = "vctcxo_1m";
+ #clock-cells = <0>;
+ };
+
+ vctcxo_24m: clock-24m {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "vctcxo_24m";
+ #clock-cells = <0>;
+ };
+
+ vctcxo_3m: clock-3m {
+ compatible = "fixed-clock";
+ clock-frequency = <3000000>;
+ clock-output-names = "vctcxo_3m";
+ #clock-cells = <0>;
+ };
+
+ osc_32k: clock-32k {
+ compatible = "fixed-clock";
+ clock-frequency = <32000>;
+ clock-output-names = "osc_32k";
+ #clock-cells = <0>;
+ };
+ };
+
soc: soc {
compatible = "simple-bus";
interrupt-parent = <&plic>;
@@ -326,96 +347,267 @@
dma-noncoherent;
ranges;
- uart0: serial at d4017000 {
- compatible = "spacemit,k1-uart", "intel,xscale-uart";
- reg = <0x0 0xd4017000 0x0 0x100>;
- interrupts = <42>;
- clock-frequency = <14857000>;
- reg-shift = <2>;
- reg-io-width = <4>;
+ syscon_rcpu: system-controller at c0880000 {
+ compatible = "spacemit,k1-syscon-rcpu";
+ reg = <0x0 0xc0880000 0x0 0x2048>;
+ #reset-cells = <1>;
+ };
+
+ syscon_rcpu2: system-controller at c0888000 {
+ compatible = "spacemit,k1-syscon-rcpu2";
+ reg = <0x0 0xc0888000 0x0 0x28>;
+ #reset-cells = <1>;
+ };
+
+ syscon_apbc: system-controller at d4015000 {
+ compatible = "spacemit,k1-syscon-apbc";
+ reg = <0x0 0xd4015000 0x0 0x1000>;
+ clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>,
+ <&vctcxo_24m>;
+ clock-names = "osc", "vctcxo_1m", "vctcxo_3m",
+ "vctcxo_24m";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ gpio: gpio at d4019000 {
+ compatible = "spacemit,k1-gpio";
+ reg = <0x0 0xd4019000 0x0 0x100>;
+ clocks = <&syscon_apbc CLK_GPIO>,
+ <&syscon_apbc CLK_GPIO_BUS>;
+ clock-names = "core", "bus";
+ gpio-controller;
+ #gpio-cells = <3>;
+ interrupts = <58>;
+ interrupt-parent = <&plic>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ gpio-ranges = <&pinctrl 0 0 0 32>,
+ <&pinctrl 1 0 32 32>,
+ <&pinctrl 2 0 64 32>,
+ <&pinctrl 3 0 96 32>;
+ };
+
+ pwm0: pwm at d401a000 {
+ compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
+ reg = <0x0 0xd401a000 0x0 0x10>;
+ #pwm-cells = <3>;
+ clocks = <&syscon_apbc CLK_PWM0>;
+ resets = <&syscon_apbc RESET_PWM0>;
+ status = "disabled";
+ };
+
+ pwm1: pwm at d401a400 {
+ compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
+ reg = <0x0 0xd401a400 0x0 0x10>;
+ #pwm-cells = <3>;
+ clocks = <&syscon_apbc CLK_PWM1>;
+ resets = <&syscon_apbc RESET_PWM1>;
+ status = "disabled";
+ };
+
+ pwm2: pwm at d401a800 {
+ compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
+ reg = <0x0 0xd401a800 0x0 0x10>;
+ #pwm-cells = <3>;
+ clocks = <&syscon_apbc CLK_PWM2>;
+ resets = <&syscon_apbc RESET_PWM2>;
+ status = "disabled";
+ };
+
+ pwm3: pwm at d401ac00 {
+ compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
+ reg = <0x0 0xd401ac00 0x0 0x10>;
+ #pwm-cells = <3>;
+ clocks = <&syscon_apbc CLK_PWM3>;
+ resets = <&syscon_apbc RESET_PWM3>;
+ status = "disabled";
+ };
+
+ pwm4: pwm at d401b000 {
+ compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
+ reg = <0x0 0xd401b000 0x0 0x10>;
+ #pwm-cells = <3>;
+ clocks = <&syscon_apbc CLK_PWM4>;
+ resets = <&syscon_apbc RESET_PWM4>;
+ status = "disabled";
+ };
+
+ pwm5: pwm at d401b400 {
+ compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
+ reg = <0x0 0xd401b400 0x0 0x10>;
+ #pwm-cells = <3>;
+ clocks = <&syscon_apbc CLK_PWM5>;
+ resets = <&syscon_apbc RESET_PWM5>;
+ status = "disabled";
+ };
+
+ pwm6: pwm at d401b800 {
+ compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
+ reg = <0x0 0xd401b800 0x0 0x10>;
+ #pwm-cells = <3>;
+ clocks = <&syscon_apbc CLK_PWM6>;
+ resets = <&syscon_apbc RESET_PWM6>;
+ status = "disabled";
+ };
+
+ pwm7: pwm at d401bc00 {
+ compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
+ reg = <0x0 0xd401bc00 0x0 0x10>;
+ #pwm-cells = <3>;
+ clocks = <&syscon_apbc CLK_PWM7>;
+ resets = <&syscon_apbc RESET_PWM7>;
+ status = "disabled";
+ };
+
+ pinctrl: pinctrl at d401e000 {
+ compatible = "spacemit,k1-pinctrl";
+ reg = <0x0 0xd401e000 0x0 0x400>;
+ clocks = <&syscon_apbc CLK_AIB>,
+ <&syscon_apbc CLK_AIB_BUS>;
+ clock-names = "func", "bus";
+ };
+
+ pwm8: pwm at d4020000 {
+ compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
+ reg = <0x0 0xd4020000 0x0 0x10>;
+ #pwm-cells = <3>;
+ clocks = <&syscon_apbc CLK_PWM8>;
+ resets = <&syscon_apbc RESET_PWM8>;
+ status = "disabled";
+ };
+
+ pwm9: pwm at d4020400 {
+ compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
+ reg = <0x0 0xd4020400 0x0 0x10>;
+ #pwm-cells = <3>;
+ clocks = <&syscon_apbc CLK_PWM9>;
+ resets = <&syscon_apbc RESET_PWM9>;
+ status = "disabled";
+ };
+
+ pwm10: pwm at d4020800 {
+ compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
+ reg = <0x0 0xd4020800 0x0 0x10>;
+ #pwm-cells = <3>;
+ clocks = <&syscon_apbc CLK_PWM10>;
+ resets = <&syscon_apbc RESET_PWM10>;
status = "disabled";
};
- uart2: serial at d4017100 {
- compatible = "spacemit,k1-uart", "intel,xscale-uart";
- reg = <0x0 0xd4017100 0x0 0x100>;
- interrupts = <44>;
- clock-frequency = <14857000>;
- reg-shift = <2>;
- reg-io-width = <4>;
+ pwm11: pwm at d4020c00 {
+ compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
+ reg = <0x0 0xd4020c00 0x0 0x10>;
+ #pwm-cells = <3>;
+ clocks = <&syscon_apbc CLK_PWM11>;
+ resets = <&syscon_apbc RESET_PWM11>;
status = "disabled";
};
- uart3: serial at d4017200 {
- compatible = "spacemit,k1-uart", "intel,xscale-uart";
- reg = <0x0 0xd4017200 0x0 0x100>;
- interrupts = <45>;
- clock-frequency = <14857000>;
- reg-shift = <2>;
- reg-io-width = <4>;
+ pwm12: pwm at d4021000 {
+ compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
+ reg = <0x0 0xd4021000 0x0 0x10>;
+ #pwm-cells = <3>;
+ clocks = <&syscon_apbc CLK_PWM12>;
+ resets = <&syscon_apbc RESET_PWM12>;
status = "disabled";
};
- uart4: serial at d4017300 {
- compatible = "spacemit,k1-uart", "intel,xscale-uart";
- reg = <0x0 0xd4017300 0x0 0x100>;
- interrupts = <46>;
- clock-frequency = <14857000>;
- reg-shift = <2>;
- reg-io-width = <4>;
+ pwm13: pwm at d4021400 {
+ compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
+ reg = <0x0 0xd4021400 0x0 0x10>;
+ #pwm-cells = <3>;
+ clocks = <&syscon_apbc CLK_PWM13>;
+ resets = <&syscon_apbc RESET_PWM13>;
status = "disabled";
};
- uart5: serial at d4017400 {
- compatible = "spacemit,k1-uart", "intel,xscale-uart";
- reg = <0x0 0xd4017400 0x0 0x100>;
- interrupts = <47>;
- clock-frequency = <14857000>;
- reg-shift = <2>;
- reg-io-width = <4>;
+ pwm14: pwm at d4021800 {
+ compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
+ reg = <0x0 0xd4021800 0x0 0x10>;
+ #pwm-cells = <3>;
+ clocks = <&syscon_apbc CLK_PWM14>;
+ resets = <&syscon_apbc RESET_PWM14>;
status = "disabled";
};
- uart6: serial at d4017500 {
- compatible = "spacemit,k1-uart", "intel,xscale-uart";
- reg = <0x0 0xd4017500 0x0 0x100>;
- interrupts = <48>;
- clock-frequency = <14857000>;
- reg-shift = <2>;
- reg-io-width = <4>;
+ pwm15: pwm at d4021c00 {
+ compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
+ reg = <0x0 0xd4021c00 0x0 0x10>;
+ #pwm-cells = <3>;
+ clocks = <&syscon_apbc CLK_PWM15>;
+ resets = <&syscon_apbc RESET_PWM15>;
status = "disabled";
};
- uart7: serial at d4017600 {
- compatible = "spacemit,k1-uart", "intel,xscale-uart";
- reg = <0x0 0xd4017600 0x0 0x100>;
- interrupts = <49>;
- clock-frequency = <14857000>;
- reg-shift = <2>;
- reg-io-width = <4>;
+ pwm16: pwm at d4022000 {
+ compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
+ reg = <0x0 0xd4022000 0x0 0x10>;
+ #pwm-cells = <3>;
+ clocks = <&syscon_apbc CLK_PWM16>;
+ resets = <&syscon_apbc RESET_PWM16>;
status = "disabled";
};
- uart8: serial at d4017700 {
- compatible = "spacemit,k1-uart", "intel,xscale-uart";
- reg = <0x0 0xd4017700 0x0 0x100>;
- interrupts = <50>;
- clock-frequency = <14857000>;
- reg-shift = <2>;
- reg-io-width = <4>;
+ pwm17: pwm at d4022400 {
+ compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
+ reg = <0x0 0xd4022400 0x0 0x10>;
+ #pwm-cells = <3>;
+ clocks = <&syscon_apbc CLK_PWM17>;
+ resets = <&syscon_apbc RESET_PWM17>;
status = "disabled";
};
- uart9: serial at d4017800 {
- compatible = "spacemit,k1-uart", "intel,xscale-uart";
- reg = <0x0 0xd4017800 0x0 0x100>;
- interrupts = <51>;
- clock-frequency = <14857000>;
- reg-shift = <2>;
- reg-io-width = <4>;
+ pwm18: pwm at d4022800 {
+ compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
+ reg = <0x0 0xd4022800 0x0 0x10>;
+ #pwm-cells = <3>;
+ clocks = <&syscon_apbc CLK_PWM18>;
+ resets = <&syscon_apbc RESET_PWM18>;
status = "disabled";
};
+ pwm19: pwm at d4022c00 {
+ compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
+ reg = <0x0 0xd4022c00 0x0 0x10>;
+ #pwm-cells = <3>;
+ clocks = <&syscon_apbc CLK_PWM19>;
+ resets = <&syscon_apbc RESET_PWM19>;
+ status = "disabled";
+ };
+
+ syscon_mpmu: system-controller at d4050000 {
+ compatible = "spacemit,k1-syscon-mpmu";
+ reg = <0x0 0xd4050000 0x0 0x209c>;
+ clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>,
+ <&vctcxo_24m>;
+ clock-names = "osc", "vctcxo_1m", "vctcxo_3m",
+ "vctcxo_24m";
+ #clock-cells = <1>;
+ #power-domain-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ pll: clock-controller at d4090000 {
+ compatible = "spacemit,k1-pll";
+ reg = <0x0 0xd4090000 0x0 0x1000>;
+ clocks = <&vctcxo_24m>;
+ spacemit,mpmu = <&syscon_mpmu>;
+ #clock-cells = <1>;
+ };
+
+ syscon_apmu: system-controller at d4282800 {
+ compatible = "spacemit,k1-syscon-apmu";
+ reg = <0x0 0xd4282800 0x0 0x400>;
+ clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>,
+ <&vctcxo_24m>;
+ clock-names = "osc", "vctcxo_1m", "vctcxo_3m",
+ "vctcxo_24m";
+ #clock-cells = <1>;
+ #power-domain-cells = <1>;
+ #reset-cells = <1>;
+ };
+
plic: interrupt-controller at e0000000 {
compatible = "spacemit,k1-plic", "sifive,plic-1.0.0";
reg = <0x0 0xe0000000 0x0 0x4000000>;
@@ -446,35 +638,201 @@
<&cpu7_intc 3>, <&cpu7_intc 7>;
};
- sec_uart1: serial at f0612000 {
- compatible = "spacemit,k1-uart", "intel,xscale-uart";
- reg = <0x0 0xf0612000 0x0 0x100>;
- interrupts = <43>;
- clock-frequency = <14857000>;
- reg-shift = <2>;
- reg-io-width = <4>;
- status = "reserved"; /* for TEE usage */
- };
-
- reset: reset-controller at d4050000 {
- compatible = "spacemit,k1-reset";
- reg = <0x0 0xd4050000 0x0 0x209c>,
- <0x0 0xd4282800 0x0 0x400>,
- <0x0 0xd4015000 0x0 0x1000>,
- <0x0 0xd4090000 0x0 0x1000>,
- <0x0 0xd4282c00 0x0 0x400>,
- <0x0 0xd8440000 0x0 0x98>,
- <0x0 0xc0000000 0x0 0x4280>,
- <0x0 0xf0610000 0x0 0x20>;
- reg-names = "mpmu", "apmu", "apbc", "apbs", "ciu", "dciu", "ddrc", "apbc2";
+ syscon_apbc2: system-controller at f0610000 {
+ compatible = "spacemit,k1-syscon-apbc2";
+ reg = <0x0 0xf0610000 0x0 0x20>;
#reset-cells = <1>;
- status = "disabled";
};
- pinctrl: pinctrl at d401e000 {
- compatible = "spacemit,k1-pinctrl", "pinctrl-single";
- reg = <0x0 0xd401e000 0x0 0x400>;
- pinctrl-single,register-width = <32>;
+ camera-bus {
+ compatible = "simple-bus";
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>,
+ <0x0 0x80000000 0x1 0x00000000 0x1 0x80000000>;
+ };
+
+ dma-bus {
+ compatible = "simple-bus";
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>,
+ <0x1 0x00000000 0x1 0x80000000 0x3 0x00000000>;
+
+ uart0: serial at d4017000 {
+ compatible = "spacemit,k1-uart",
+ "intel,xscale-uart";
+ reg = <0x0 0xd4017000 0x0 0x100>;
+ clocks = <&syscon_apbc CLK_UART0>,
+ <&syscon_apbc CLK_UART0_BUS>;
+ clock-names = "core", "bus";
+ interrupts = <42>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart2: serial at d4017100 {
+ compatible = "spacemit,k1-uart",
+ "intel,xscale-uart";
+ reg = <0x0 0xd4017100 0x0 0x100>;
+ clocks = <&syscon_apbc CLK_UART2>,
+ <&syscon_apbc CLK_UART2_BUS>;
+ clock-names = "core", "bus";
+ interrupts = <44>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart3: serial at d4017200 {
+ compatible = "spacemit,k1-uart",
+ "intel,xscale-uart";
+ reg = <0x0 0xd4017200 0x0 0x100>;
+ clocks = <&syscon_apbc CLK_UART3>,
+ <&syscon_apbc CLK_UART3_BUS>;
+ clock-names = "core", "bus";
+ interrupts = <45>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart4: serial at d4017300 {
+ compatible = "spacemit,k1-uart",
+ "intel,xscale-uart";
+ reg = <0x0 0xd4017300 0x0 0x100>;
+ clocks = <&syscon_apbc CLK_UART4>,
+ <&syscon_apbc CLK_UART4_BUS>;
+ clock-names = "core", "bus";
+ interrupts = <46>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart5: serial at d4017400 {
+ compatible = "spacemit,k1-uart",
+ "intel,xscale-uart";
+ reg = <0x0 0xd4017400 0x0 0x100>;
+ clocks = <&syscon_apbc CLK_UART5>,
+ <&syscon_apbc CLK_UART5_BUS>;
+ clock-names = "core", "bus";
+ interrupts = <47>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart6: serial at d4017500 {
+ compatible = "spacemit,k1-uart",
+ "intel,xscale-uart";
+ reg = <0x0 0xd4017500 0x0 0x100>;
+ clocks = <&syscon_apbc CLK_UART6>,
+ <&syscon_apbc CLK_UART6_BUS>;
+ clock-names = "core", "bus";
+ interrupts = <48>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart7: serial at d4017600 {
+ compatible = "spacemit,k1-uart",
+ "intel,xscale-uart";
+ reg = <0x0 0xd4017600 0x0 0x100>;
+ clocks = <&syscon_apbc CLK_UART7>,
+ <&syscon_apbc CLK_UART7_BUS>;
+ clock-names = "core", "bus";
+ interrupts = <49>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart8: serial at d4017700 {
+ compatible = "spacemit,k1-uart",
+ "intel,xscale-uart";
+ reg = <0x0 0xd4017700 0x0 0x100>;
+ clocks = <&syscon_apbc CLK_UART8>,
+ <&syscon_apbc CLK_UART8_BUS>;
+ clock-names = "core", "bus";
+ interrupts = <50>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart9: serial at d4017800 {
+ compatible = "spacemit,k1-uart",
+ "intel,xscale-uart";
+ reg = <0x0 0xd4017800 0x0 0x100>;
+ clocks = <&syscon_apbc CLK_UART9>,
+ <&syscon_apbc CLK_UART9_BUS>;
+ clock-names = "core", "bus";
+ interrupts = <51>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ sec_uart1: serial at f0612000 {
+ compatible = "spacemit,k1-uart",
+ "intel,xscale-uart";
+ reg = <0x0 0xf0612000 0x0 0x100>;
+ interrupts = <43>;
+ clock-frequency = <14857000>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "reserved"; /* for TEE usage */
+ };
+ };
+
+ multimedia-bus {
+ compatible = "simple-bus";
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>,
+ <0x0 0x80000000 0x1 0x00000000 0x3 0x80000000>;
+ };
+
+ network-bus {
+ compatible = "simple-bus";
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>,
+ <0x0 0x80000000 0x1 0x00000000 0x0 0x80000000>;
+ };
+
+ pcie-bus {
+ compatible = "simple-bus";
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>,
+ <0x0 0xb8000000 0x1 0x38000000 0x3 0x48000000>;
+ };
+
+ storage-bus {
+ compatible = "simple-bus";
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>;
+
+ emmc: mmc at d4281000 {
+ compatible = "spacemit,k1-sdhci";
+ reg = <0x0 0xd4281000 0x0 0x200>;
+ clocks = <&syscon_apmu CLK_SDH_AXI>,
+ <&syscon_apmu CLK_SDH2>;
+ clock-names = "core", "io";
+ interrupts = <101>;
+ status = "disabled";
+ };
};
};
};
--
2.25.1
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