[PATCH master] mach-k3: am64x: add support for speed grades

[Anshul Dalal]

With the support for common speed grade configuration added in commit
65a6b83a9b7f ("mach-k3: refactor A53 speed grade clock-rate fixup"),
this patch extends the support to AM64x SoCs.

Signed-off-by: Anshul Dalal <anshuld at ti.com>
---
 arch/arm/mach-k3/am64x/am642_init.c           | 22 ++++++++++++++++++++++
 arch/arm/mach-k3/include/mach/am64_hardware.h |  4 ++++
 2 files changed, 26 insertions(+)

diff --git a/arch/arm/mach-k3/am64x/am642_init.c b/arch/arm/mach-k3/am64x/am642_init.c
index 219798315db..a15adf1cb1e 100644
--- a/arch/arm/mach-k3/am64x/am642_init.c
+++ b/arch/arm/mach-k3/am64x/am642_init.c
@@ -29,6 +29,26 @@
 #define SW_POR_MCU                             BIT(24)
 #define SW_POR_MAIN                            BIT(25)
 
+const struct k3_speed_grade_map am64_map[] = {
+	{'S', 1000000000},
+	{'K', 800000000},
+	{/* List Terminator */ },
+};
+
+char k3_get_speed_grade(void)
+{
+	u32 efuse_val = readl(CTRLMMR_WKUP_JTAG_DEVICE_ID);
+	u32 efuse_speed = (efuse_val & JTAG_DEV_SPEED_MASK) >>
+			  JTAG_DEV_SPEED_SHIFT;
+
+	return ('A' - 1) + efuse_speed;
+}
+
+const struct k3_speed_grade_map *k3_get_speed_grade_map(void)
+{
+	return am64_map;
+}
+
 static void ctrl_mmr_unlock(void)
 {
 	/* Unlock all PADCFG_MMR1 module registers */
@@ -263,6 +283,8 @@ void board_init_f(ulong dummy)
 	if (ret)
 		panic("DRAM init failed: %d\n", ret);
 #endif
+
+	k3_fix_rproc_clock("/a53 at 0");
 }
 
 u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
diff --git a/arch/arm/mach-k3/include/mach/am64_hardware.h b/arch/arm/mach-k3/include/mach/am64_hardware.h
index 2717da07690..7e33617151e 100644
--- a/arch/arm/mach-k3/include/mach/am64_hardware.h
+++ b/arch/arm/mach-k3/include/mach/am64_hardware.h
@@ -18,6 +18,10 @@
 #define MCU_CTRL_MMR0_BASE				0x04500000
 #define CTRL_MMR0_BASE					0x43000000
 
+#define CTRLMMR_WKUP_JTAG_DEVICE_ID		(WKUP_CTRL_MMR0_BASE + 0x18)
+#define JTAG_DEV_SPEED_MASK			GENMASK(10, 6)
+#define JTAG_DEV_SPEED_SHIFT			6
+
 #define CTRLMMR_MAIN_DEVSTAT				(CTRL_MMR0_BASE + 0x30)
 
 #define MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK		0x00000078

---
base-commit: 51a884fdf3a9f88f3bbd0e4b1782cc6eb172b8a9
change-id: 20260121-am64x_speed_grade-1c71f7ad43dc

Best regards,
-- 
Anshul Dalal <anshuld at ti.com>