[PATCH v1 3/3] arm: agilex5: Enable eMMC HS200 and HS400 mode support

[Tanmay Kathpalia]

On 1/26/2026 1:53 AM, Tanmay Kathpalia wrote:
> Enable high-speed eMMC modes on Agilex5 SoC development kit for
> improved storage performance.
> 
> Defconfig changes:
> - Enable CONFIG_MMC_HS400_SUPPORT and CONFIG_SPL_MMC_HS400_SUPPORT
> 
> Device tree changes:
> - Add mmc-hs200-1_8v and mmc-hs400-1_8v capabilities
> - Add sdhci-caps-mask to mask SDHCI_CLOCK_V3_BASE_MASK bits
> - Add sdhci-caps to set 200MHz base clock and 8-bit bus width
> - Add PHY and controller timing configuration for HS200 mode
> - Add PHY and controller timing configuration for HS400 mode
> 
> Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia at altera.com>
> ---
>   arch/arm/dts/socfpga_agilex5_socdk_emmc.dts | 28 ++++++++++++++++++++-
>   configs/socfpga_agilex5_emmc_defconfig      |  2 ++
>   2 files changed, 29 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/dts/socfpga_agilex5_socdk_emmc.dts b/arch/arm/dts/socfpga_agilex5_socdk_emmc.dts
> index f6848c373cd..49b4a85783c 100644
> --- a/arch/arm/dts/socfpga_agilex5_socdk_emmc.dts
> +++ b/arch/arm/dts/socfpga_agilex5_socdk_emmc.dts
> @@ -1,6 +1,6 @@
>   // SPDX-License-Identifier:     GPL-2.0
>   /*
> - * Copyright (C) 2025 Altera Corporation <www.altera.com>
> + * Copyright (C) 2025-2026 Altera Corporation <www.altera.com>
>    */
>   
>   #include "socfpga_agilex5_socdk.dts"
> @@ -25,11 +25,15 @@
>   	disable-wp;
>   	non-removable;
>   	cap-mmc-highspeed;
> +	mmc-hs200-1_8v;
> +	mmc-hs400-1_8v;
>   
>   	bus-width = <8>;
>   	vmmc-supply = <&sd_emmc_power>;
>   	vqmmc-supply = <&emmc_io_1v8_reg>;
>   	max-frequency = <200000000>;
> +	sdhci-caps = <0x00000000 0x0004c800>;	/* SDHCI_CAN_DO_8BIT */
> +	sdhci-caps-mask = <0x00000000 0x0000ff00>;
>   
>   	/* eMMC legacy mode timing configuration */
>   	cdns,phy-dqs-timing-delay-sd-ds = <0x00780000>;
> @@ -46,4 +50,26 @@
>   	cdns,ctrl-hrs10-lpbk-ctrl-delay-emmc-sdr = <0x30000>;
>   	cdns,ctrl-hrs16-slave-ctrl-emmc-sdr = <0x101>;
>   	cdns,ctrl-hrs07-timing-delay-emmc-sdr = <0xA0001>;
> +
> +	/* eMMC HS200 mode timing configuration */
> +	cdns,phy-dq-timing-delay-emmc-hs200 = <0x10000001>;
> +	cdns,phy-dqs-timing-delay-emmc-hs200 = <0x780004>;
> +	cdns,phy-dll-slave-ctrl-emmc-hs200 = <0x4d4d00>;
> +	cdns,phy-gate-lpbk-ctrl-delay-emmc-hs200 = <0x81a40040>;
> +	cdns,phy-dll-master-ctrl-emmc-hs200 = <0x4>;
> +	cdns,ctrl-hrs09-timing-delay-emmc-hs200 = <0xf1c18000>;
> +	cdns,ctrl-hrs10-lpbk-ctrl-delay-emmc-hs200 = <0x90000>;
> +	cdns,ctrl-hrs16-slave-ctrl-emmc-hs200 = <0x101>;
> +	cdns,ctrl-hrs07-timing-delay-emmc-hs200 = <0xa0001>;
> +
> +	/* eMMC HS400 mode timing configuration */
> +	cdns,phy-dq-timing-delay-emmc-hs400 = <0x10000001>;
> +	cdns,phy-dqs-timing-delay-emmc-hs400 = <0x680004>;
> +	cdns,phy-dll-slave-ctrl-emmc-hs400 = <0x4d4b40>;
> +	cdns,phy-gate-lpbk-ctrl-delay-emmc-hs400 = <0x81a40040>;
> +	cdns,phy-dll-master-ctrl-emmc-hs400 = <0x4>;
> +	cdns,ctrl-hrs09-timing-delay-emmc-hs400 = <0xf1c18000>;
> +	cdns,ctrl-hrs10-lpbk-ctrl-delay-emmc-hs400 = <0x80000>;
> +	cdns,ctrl-hrs16-slave-ctrl-emmc-hs400 = <0x11000001>;
> +	cdns,ctrl-hrs07-timing-delay-emmc-hs400 = <0x90001>;
>   };
> diff --git a/configs/socfpga_agilex5_emmc_defconfig b/configs/socfpga_agilex5_emmc_defconfig
> index 9254ab92e0c..d2d359cd1d4 100644
> --- a/configs/socfpga_agilex5_emmc_defconfig
> +++ b/configs/socfpga_agilex5_emmc_defconfig
> @@ -4,3 +4,5 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex5_socdk_emmc"
>   # CONFIG_SPL_DM_REGULATOR_GPIO is not set
>   # CONFIG_DM_REGULATOR_GPIO is not set
>   # CONFIG_SPL_DWAPB_GPIO is not set
> +CONFIG_MMC_HS400_SUPPORT=y
> +CONFIG_SPL_MMC_HS400_SUPPORT=y
> \ No newline at end of file

Add newline at end of file.