[PATCH v2 14/24] clk: clk-composite: Resolve parent clock by name

[Simon Glass]

Hi Heinrich,

On Mon, 31 Mar 2025 at 05:14, Heinrich Schuchardt
<heinrich.schuchardt at canonical.com> wrote:
>
> On 30.03.25 17:15, Heinrich Schuchardt wrote:
> > On 23.03.25 16:58, Marek Vasut wrote:
> >> Use clock-names property which is accessible via parent clock OF node
> >> to look up the parent clock by name instead of depending on unreliable
> >> global clock name to perform look up.
> >>
> >> Signed-off-by: Marek Vasut <marex at denx.de>
> >
> > This patch breaks booting starfive_visionfive2_defconfig in the SPL stage.
> >
> > To dig a bit deeper I enabled the debug UART for SPL with these setting
> > on origin/master (5e74863ad6613df):
> >
> > CONFIG_DEBUG_UART=y
> > CONFIG_DEBUG_UART_NS16550=y
> > CONFIG_DEBUG_UART_BASE=0x10000000
> > CONFIG_DEBUG_UART_CLOCK=24000000
> > CONFIG_SPL_DEBUG_UART_BASE=0x10000000
> > CONFIG_DEBUG_UART_SHIFT=2
> >
> > clk_register: failed to get pll0_out device (parent of perh_root)
> > clk_register: failed to get pll0_out device (parent of qspi_ref_src)
> > clk_register: failed to get pll0_out device (parent of usb_125m)
> > clk_register: failed to get pll0_out device (parent of gmac_src)
> > clk_register: failed to get pll0_out device (parent of gmac1_gtxclk)
> > clk_register: failed to get pll0_out device (parent of gmac0_gtxclk)
> >
> > Marek assumes that property bootph-pre-ram might be missing for some
> > clocks in arch/riscv/dts/jh7110-u-boot.dtsi.
>
> This change suggested by Marek resolves the issue:
>
> diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi
> b/arch/riscv/dts/jh7110-u-boot.dtsi
> index ce7d9e16961..4ed764393bb 100644
> --- a/arch/riscv/dts/jh7110-u-boot.dtsi
> +++ b/arch/riscv/dts/jh7110-u-boot.dtsi
> @@ -113,3 +113,7 @@
>   &sys_syscon {
>          bootph-pre-ram;
>   };
> +
> +&pllclk {
> +       bootph-pre-ram;
> +};

I just hit this as well, thanks for the post.

However, -master still does not boot for me on vf2:

U-Boot SPL 2026.04-rc1 (Jan 26 2026 - 19:52:48 -0700)
DDR version: dc2e84f0.
Trying to boot from MMC2
spl: partition error
Error: -38
SPL: Unsupported Boot Device!
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###

Regards,
Simon

>
> >
> >> ---
> >> Cc: Adam Ford <aford173 at gmail.com>
> >> Cc: Christoph Niedermaier <cniedermaier at dh-electronics.com>
> >> Cc: Dong Aisheng <aisheng.dong at nxp.com>
> >> Cc: Fabio Estevam <festevam at denx.de>
> >> Cc: Hou Zhiqiang <Zhiqiang.Hou at nxp.com>
> >> Cc: Michael Trimarchi <michael at amarulasolutions.com>
> >> Cc: Peng Fan <peng.fan at nxp.com>
> >> Cc: Tim Harvey <tharvey at gateworks.com>
> >> Cc: Tom Rini <trini at konsulko.com>
> >> Cc: u-boot at lists.denx.de
> >> Cc: uboot-imx at nxp.com
> >> ---
> >> V2: Rebase on u-boot/next with additional clock patches
> >> ---
> >>   drivers/clk/clk-composite.c | 2 +-
> >>   1 file changed, 1 insertion(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
> >> index 1191bdf87df..9e3b5191767 100644
> >> --- a/drivers/clk/clk-composite.c
> >> +++ b/drivers/clk/clk-composite.c
> >> @@ -149,7 +149,7 @@ struct clk *clk_register_composite(struct udevice
> >> *dev, const char *name,
> >>       clk = &composite->clk;
> >>       clk->flags = flags;
> >>       ret = clk_register(clk, UBOOT_DM_CLK_COMPOSITE, name,
> >> -               parent_names[clk_composite_get_parent(clk)]);
> >> +        clk_resolve_parent_clk(dev,
> >> parent_names[clk_composite_get_parent(clk)]));
> >>       if (ret) {
> >>           clk = ERR_PTR(ret);
> >>           goto err;
> >
>