[PATCH V2 4/4] usb: dwc3: core: improve reset sequence

[Mattijs Korpershoek]

Hi Chris,

Thank you for the patch.

On Thu, Jan 15, 2026 at 17:01, Chris Morgan <macroalpha82 at gmail.com> wrote:

> From: Chris Morgan <macromorgan at hotmail.com>
>
> According to Synopsys Databook, we shouldn't be
> relying on GCTL.CORESOFTRESET bit as that's only for
> debugging purposes. Instead, let's use DCTL.CSFTRST
> if we're OTG or PERIPHERAL mode.
>
> Host side block will be reset by XHCI driver if
> necessary. Note that this reduces amount of time
> spent on dwc3_probe() by a long margin.
>
> We're still gonna wait for reset to finish for a
> long time (default to 1ms max), but tests show that
> the reset polling loop executed at most 19 times
> (modprobe dwc3 && modprobe -r dwc3 executed 1000
> times in a row).
>
> Note that this patch was submitted to Linux in 2016 [1], however I can
> confirm it is needed to support gadget mode in U-Boot on my device.
> While I am referencing this patch from Linux I am in fact taking the
> full existing dwc3_core_soft_reset() function from Linux as it exists
> in v6.19-rc5, so it may differ slightly from the information in the
> 2016 patch.
>
> [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/patch/drivers/usb/dwc3?id=f59dcab176293b646e1358144c93c58c3cda2813
>
> Suggested-by: Mian Yousaf Kaukab <yousaf.kaukab at intel.com>
> Signed-off-by: Felipe Balbi <felipe.balbi at linux.intel.com>
> Signed-off-by: Chris Morgan <macromorgan at hotmail.com>

Reviewed-by: Mattijs Korpershoek <mkorpershoek at kernel.org>

> ---
>  drivers/usb/dwc3/core.c | 66 ++++++++++++++++++++++++-----------------
>  1 file changed, 39 insertions(+), 27 deletions(-)
>