[PATCH v4 2/7] arm: dts: socfpga: n5x: update GMAC nodes and DT register settings

[Chee, Tien Fong]

On 23/6/2026 10:02 am, Chen Huei Lok wrote:
> Enable register settings in the N5X U-Boot device tree by adding
> firewall configuration nodes under the L3 interconnect firewall.
> These settings disable OCRAM security at the CCU and relax MPFE
> firewall restrictions required during early boot.
>
> Update the GMAC nodes to include proper compatible,
> reset-names, and clock-names properties, explicitly setting
> their status.
>
> Remove the clocks property from the QSPI node in
> socfpga_n5x_socdk-u-boot.dtsi. The QSPI controller clock is obtained
> via cm_get_qspi_controller_clk_hz(), so the device tree clock
> reference is unnecessary.
>
> Additionally, include socfpga_soc64_u-boot.dtsi and rename the
> soc node to soc at 0 in socfpga_n5x-u-boot.dtsi to align with
> the common SoCFPGA DT layout.
>
> Signed-off-by: Tien Fong Chee <tien.fong.chee at altera.com>
> Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi at altera.com>
> Signed-off-by: Chen Huei Lok <chen.huei.lok at altera.com>
> ---
>   arch/arm/dts/socfpga_n5x-u-boot.dtsi       | 38 +++++++++++++++++++++-
>   arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi |  5 +++
>   2 files changed, 42 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/dts/socfpga_n5x-u-boot.dtsi b/arch/arm/dts/socfpga_n5x-u-boot.dtsi
> index e27a64651e1..dbfd2abfd59 100644
> --- a/arch/arm/dts/socfpga_n5x-u-boot.dtsi
> +++ b/arch/arm/dts/socfpga_n5x-u-boot.dtsi
> @@ -5,6 +5,7 @@
>    * Copyright (C) 2020-2021 Intel Corporation <www.intel.com>
>    */
>   
> +#include "socfpga_soc64_u-boot.dtsi"
>   #include "socfpga_soc64_fit-u-boot.dtsi"
>   #include <dt-bindings/clock/n5x-clock.h>
>   
> @@ -15,7 +16,7 @@
>   		bootph-all;
>   	};
>   
> -	soc {
> +	soc at 0 {
>   		bootph-all;
>   
>   		ccu: cache-controller at f7000000 {
> @@ -46,17 +47,29 @@
>   };
>   
>   &gmac0 {
> +	compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
> +	reset-names = "stmmaceth", "stmmaceth-ocp";
>   	clocks = <&clkmgr N5X_EMAC0_CLK>;
> +	clock-names = "stmmaceth";
> +	status = "disabled";
>   };
>   
>   &gmac1 {
> +	compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
> +	reset-names = "stmmaceth", "stmmaceth-ocp";
>   	altr,sysmgr-syscon = <&sysmgr 0x48 0>;
>   	clocks = <&clkmgr N5X_EMAC1_CLK>;
> +	clock-names = "stmmaceth";
> +	status = "disabled";
>   };
>   
>   &gmac2 {
> +	compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
> +	reset-names = "stmmaceth", "stmmaceth-ocp";
>   	altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
>   	clocks = <&clkmgr N5X_EMAC2_CLK>;
> +	clock-names = "stmmaceth";
> +	status = "disabled";
>   };
>   
>   &i2c0 {
> @@ -132,6 +145,29 @@
>   	clocks = <&clkmgr N5X_L4_MAIN_CLK>;
>   };
>   
> +&socfpga_l3interconnect_firewall {
> +	ocram-firewall at f7100200 {
> +		reg = <0xf7100200 0x00000014>;
> +		intel,offset-settings =
> +			/* Disable ocram security at CCU for non secure access */
> +			<0x00000004 0x8000ffff 0xe007ffff>,
> +			<0x00000008 0x8000ffff 0xe007ffff>,
> +			<0x0000000c 0x8000ffff 0xe007ffff>,
> +			<0x00000010 0x8000ffff 0xe007ffff>;
> +		bootph-all;
> +	};
> +
> +	mpfe-firewall at f8020000 {
> +		reg = <0xf8020000 0x0000001c>;
> +		intel,offset-settings =
> +			/* Disable MPFE firewall for SMMU */
> +			<0x00000000 0x00010101 0x00010101>,
> +			/* Disable MPFE firewall for HMC adapter */
> +			<0x00000004 0x00000001 0x00010101>;
> +		bootph-all;
> +	};
> +};
> +
>   &sysmgr {
>   	compatible = "altr,sys-mgr", "syscon";
>   	bootph-all;
> diff --git a/arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi
> index 840537c9d0b..1f7e31bcae3 100644
> --- a/arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi
> +++ b/arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi
> @@ -44,6 +44,10 @@
>   	bootph-all;
>   };
>   
> +&gmac0 {
> +	status = "okay";
> +};
> +
>   &i2c1 {
>   	status = "okay";
>   };
> @@ -55,6 +59,7 @@
>   };
>   
>   &qspi {
> +	/delete-property/ clocks;
>   	status = "okay";
>   };
>   


Reviewed-by: Tien Fong Chee <tien.fong.chee at altera.com>

Best regards,
Tien Fong