[PATCH v1 1/2] arch: arm: dts: socfpga: Update L4_SYS Security Control Register size

[Chee, Tien Fong]

Hi Boon Khai,

On 25/2/2026 11:21 am, Boon Khai Ng wrote:
> From: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi at altera.com>
>
> noc_fw_tcu_tcu_scr register has a base address of 0xFFD21400 and an end
> address of 0xFFD214FF for Agilex7/7M and Stratix10, which makes the size of
> the register a total of 256 bytes.
>
> Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi at altera.com>
> Signed-off-by: Boon Khai Ng <boon.khai.ng at altera.com>
> ---
>   arch/arm/dts/socfpga_soc64_u-boot.dtsi | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/dts/socfpga_soc64_u-boot.dtsi b/arch/arm/dts/socfpga_soc64_u-boot.dtsi
> index ce5b37ef547..a6e0b615717 100644
> --- a/arch/arm/dts/socfpga_soc64_u-boot.dtsi
> +++ b/arch/arm/dts/socfpga_soc64_u-boot.dtsi
> @@ -132,7 +132,7 @@
>   
>   			/* TCU */
>   			noc_fw_tcu_tcu_scr at ffd21400 {
> -				reg = <0xffd21400 0x00000004>;
> +				reg = <0xffd21400 0x00000100>;
>   				intel,offset-settings =
>   					<0x00000000 0x01010001 0x01010001>;
>   				bootph-all;


The patch updates noc_fw_tcu_tcu_scr at ffd21400 under 
socfpga_smmu_secure_config (line 134) but leaves the duplicate under 
socfpga_l3interconnect_firewall (line 111) at reg = <0xffd21400 0x00000004>.

Both nodes program the same physical register at offset 0 today, so 
runtime is unchanged. DT is inconsistent; a future offset-settings entry 
in the l3 block would hit the driver's blk_sz overflow check.

Fix: In patch 1/2, also set line 112 to <0xffd21400 0x00000100>

Best regards,
Tien Fong