[PATCH 2/9] clk: mediatek: mt8189: convert to mtk_gate_clk_data

[Julien Stephan]

MT8189 already uses a single generic clock gate driver shared across
multiple compatible strings, but relies on MT8189-specific data
structures to describe each controller.

Convert the driver to use the generic mtk_gate_clk_data infrastructure
introduced in the previous commit.

This serves as the first user of the generic framework.

No functional change is intended.

Signed-off-by: Julien Stephan <jstephan at baylibre.com>
---
 drivers/clk/mediatek/clk-mt8189.c | 26 ++++++++------------------
 1 file changed, 8 insertions(+), 18 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt8189.c b/drivers/clk/mediatek/clk-mt8189.c
index 3093fac23ce..e78c9fc0eb9 100644
--- a/drivers/clk/mediatek/clk-mt8189.c
+++ b/drivers/clk/mediatek/clk-mt8189.c
@@ -1990,23 +1990,13 @@ static const struct udevice_id mt8189_vlpckgen[] = {
 	{ }
 };
 
-struct mt8189_gate_clk_data {
-	const struct mtk_gate *gates;
-	int num_gates;
-};
-
-#define GATE_CLK_DATA(name) \
-static const struct mt8189_gate_clk_data name##_data = { \
-	.gates = name, .num_gates = ARRAY_SIZE(name) \
-}
-
-GATE_CLK_DATA(perao_clks);
-GATE_CLK_DATA(imp_clks);
-GATE_CLK_DATA(mm_clks);
-GATE_CLK_DATA(mminfra_config_clks);
-GATE_CLK_DATA(ufs_config_ao_clks);
-GATE_CLK_DATA(ufs_config_pdn_clks);
-GATE_CLK_DATA(vlpcfg_ao_clks);
+MTK_GATE_CLK_DATA(perao_clks);
+MTK_GATE_CLK_DATA(imp_clks);
+MTK_GATE_CLK_DATA(mm_clks);
+MTK_GATE_CLK_DATA(mminfra_config_clks);
+MTK_GATE_CLK_DATA(ufs_config_ao_clks);
+MTK_GATE_CLK_DATA(ufs_config_pdn_clks);
+MTK_GATE_CLK_DATA(vlpcfg_ao_clks);
 
 static const struct udevice_id of_match_mt8189_clk_gate[] = {
 	{ .compatible = "mediatek,mt8189-peri-ao", .data = (ulong)&perao_clks_data },
@@ -2036,7 +2026,7 @@ static int mt8189_infrasys_probe(struct udevice *dev)
 
 static int mt8189_clk_gate_probe(struct udevice *dev)
 {
-	struct mt8189_gate_clk_data *data;
+	struct mtk_gate_clk_data *data;
 
 	data = (void *)dev_get_driver_data(dev);
 

-- 
2.54.0