[PATCH] sysreset: esp32: add driver for esp32 series chips

[hehongbo918 at gmail.com]

From: Honbo He <hehongbo918 at gmail.com>

Add system reset driver for Espressif Gen3 and Gen4 RISC-V SoCs.
The reset register base address, offset, and bit mask are read
from the device tree to support different chip variants without
code changes.

Signed-off-by: Honbo He <hehongbo918 at gmail.com>
---
 drivers/sysreset/Kconfig          |  9 ++++
 drivers/sysreset/Makefile         |  1 +
 drivers/sysreset/sysreset_esp32.c | 72 +++++++++++++++++++++++++++++++
 3 files changed, 82 insertions(+)
 create mode 100644 drivers/sysreset/sysreset_esp32.c

diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
index 16ef434a8d9..40293442e1c 100644
--- a/drivers/sysreset/Kconfig
+++ b/drivers/sysreset/Kconfig
@@ -64,6 +64,15 @@ config SYSRESET_CV1800B
 	help
 	  Enable system reset support for Sophgo cv1800b SoC.
 
+config SYSRESET_ESP32
+	bool "Enable support for Espressif esp32 System Reset"
+	help
+	  Enable system reset support for Espressif Gen3 and Gen4
+	  SoCs (C5, C6, C61, H2, H21, H4, P4, S31) Reset register parameters
+	  are configured via device tree.
+	  Gen1/Gen2 chips (ESP32, S2, S3, C2, C3) are not supported
+	  as they rely on the boot ROM for system reset.
+
 config POWEROFF_GPIO
 	bool "Enable support for GPIO poweroff driver"
 	depends on DM_GPIO
diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
index d18a5d52360..ba3ac235658 100644
--- a/drivers/sysreset/Makefile
+++ b/drivers/sysreset/Makefile
@@ -33,3 +33,4 @@ obj-$(CONFIG_SYSRESET_RAA215300) += sysreset_raa215300.o
 obj-$(CONFIG_SYSRESET_QCOM_PSHOLD) += sysreset_qcom-pshold.o
 obj-$(CONFIG_TARGET_XTFPGA) += sysreset_xtfpga.o
 obj-$(CONFIG_SYSRESET_QEMU_VIRT_CTRL) += sysreset_qemu_virt_ctrl.o
+obj-$(CONFIG_SYSRESET_ESP32) += sysreset_esp32.o
diff --git a/drivers/sysreset/sysreset_esp32.c b/drivers/sysreset/sysreset_esp32.c
new file mode 100644
index 00000000000..3d4c619f44f
--- /dev/null
+++ b/drivers/sysreset/sysreset_esp32.c
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2026, Honbo He <hehongbo918 at gmail.com>
+ *
+ * System reset driver for Espressif SoCs.
+ *
+ * Supported SoCs (Gen3/4):
+ *  ESP32-C5, ESP32-C6, ESP32-C61, ESP32-H2, ESP32-H21, ESP32-H4,
+ *  ESP32-P4, ESP32-S31
+ *
+ * On the unsupported chips(Gen1/2), the system reset logic resides inside the
+ * RTC_CNTL peripheral and is only accessible through the boot ROM function
+ * software_reset_cpu(). The register definitions are not exposed in the SoC headers,
+ * making it impractical to implement a direct register-based reset
+ * in U-Boot without reverse-engineering the ROM code.
+ */
+
+#include <dm.h>
+#include <stdbool.h>
+#include <sysreset.h>
+#include <wait_bit.h>
+#include <linux/io.h>
+#include <linux/errno.h>
+
+struct esp32_sysreset_priv {
+	void __iomem *base;
+	u32 offset;
+	u32 mask;
+};
+
+static int esp32_sysreset_request(struct udevice *dev, enum sysreset_t type)
+{
+	struct esp32_sysreset_priv *priv = dev_get_priv(dev);
+
+	setbits_le32(priv->base + priv->offset, priv->mask);
+
+	return -EINPROGRESS;
+}
+
+static struct sysreset_ops esp32_sysreset = {
+	.request = esp32_sysreset_request,
+};
+
+static int esp32_sysreset_probe(struct udevice *dev)
+{
+	struct esp32_sysreset_priv *priv = dev_get_priv(dev);
+
+	priv->base = dev_read_addr_ptr(dev);
+	if (!priv->base)
+		return -EINVAL;
+
+	priv->offset = dev_read_u32_default(dev, "offset", 0);
+	priv->mask = dev_read_u32_default(dev, "mask", 0);
+	if (priv->mask == 0)
+		return -EINVAL;
+
+	return 0;
+}
+
+static const struct udevice_id esp32s31_sysreset_ids[] = {
+	{ .compatible = "esp,esp32-sysreset", },
+	{},
+};
+
+U_BOOT_DRIVER(sysreset_esp32) = {
+	.name = "esp32s31_sysreset",
+	.id	  = UCLASS_SYSRESET,
+	.ops  = &esp32_sysreset,
+	.of_match = esp32s31_sysreset_ids,
+	.probe = esp32_sysreset_probe,
+	.priv_auto = sizeof(struct esp32_sysreset_priv),
+};
-- 
2.34.1