[PATCH v1] serial: msm-geni: configure RX watermark register

[Sumit Garg]

On Tue, Apr 21, 2026 at 10:15:55AM +0530, Gurumoorthy Santhakumar wrote:
> From: Timple Raj M <quic_timple at quicinc.com>
> 
> The SE_GENI_RX_WATERMARK_REG was not being programmed in the RX
> setup paths. Set it to DEF_RX_WM (2) in qcom_geni_serial_start_rx(),
> msm_geni_serial_setup_rx() and _debug_uart_init() to align with the
> Linux kernel driver behaviour.
> 
> Without this, the RX FIFO watermark interrupt threshold is left at
> its hardware reset value, which may differ from the expected value
> and can cause RX data loss or missed watermark interrupts.
> 
> Link: https://lore.kernel.org/all/20200227132223.864425794@linuxfoundation.org/
> Signed-off-by: Timple Raj M <quic_timple at quicinc.com>
> Signed-off-by: Gurumoorthy Santhakumar <gurumoorthy.santhakumar at oss.qualcomm.com>
> ---
>  drivers/serial/serial_msm_geni.c | 4 ++++
>  1 file changed, 4 insertions(+)

Reviewed-by: Sumit Garg <sumit.garg at oss.qualcomm.com>

-Sumit

> 
> diff --git a/drivers/serial/serial_msm_geni.c b/drivers/serial/serial_msm_geni.c
> index 3dca581f68f..ae4015e0fdc 100644
> --- a/drivers/serial/serial_msm_geni.c
> +++ b/drivers/serial/serial_msm_geni.c
> @@ -55,6 +55,7 @@
>  #define SE_UART_RX_PARITY_CFG	0x2a8
>  
>  #define DEF_TX_WM	2
> +#define DEF_RX_WM	2
>  /* GENI_FORCE_DEFAULT_REG fields */
>  
>  #define UART_START_READ	0x1
> @@ -345,6 +346,7 @@ static void qcom_geni_serial_start_rx(struct udevice *dev)
>  
>  	geni_se_setup_s_cmd(priv->base, UART_START_READ, 0);
>  
> +	writel(DEF_RX_WM, priv->base + SE_GENI_RX_WATERMARK_REG);
>  	setbits_le32(priv->base + SE_GENI_S_IRQ_EN, S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN);
>  	setbits_le32(priv->base + SE_GENI_M_IRQ_EN, M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);
>  }
> @@ -373,6 +375,7 @@ static void msm_geni_serial_setup_rx(struct udevice *dev)
>  
>  	geni_se_setup_s_cmd(priv->base, UART_START_READ, 0);
>  
> +	writel(DEF_RX_WM, priv->base + SE_GENI_RX_WATERMARK_REG);
>  	setbits_le32(priv->base + SE_GENI_S_IRQ_EN, S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN);
>  	setbits_le32(priv->base + SE_GENI_M_IRQ_EN, M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);
>  }
> @@ -616,6 +619,7 @@ static inline void _debug_uart_init(void)
>  	phys_addr_t base = CONFIG_VAL(DEBUG_UART_BASE);
>  
>  	geni_serial_init(&init_dev);
> +	writel(DEF_RX_WM, base + SE_GENI_RX_WATERMARK_REG);
>  	geni_serial_baud(base, CLK_DIV, CONFIG_BAUDRATE);
>  	qcom_geni_serial_start_tx(base);
>  }
> -- 
> 2.34.1
>