[PATCH] riscv: Disable -fpic for SPL builds

[Yao Zi]

On Thu, Apr 30, 2026 at 01:59:07PM +0200, Michal Simek wrote:
> When building U-Boot SPL for RISC-V with position-independent code
> (-fpic), the linker fails with relocation errors like:
> 
>   relocation truncated to fit: R_RISCV_PCREL_HI20 against `symbol'
> 
> This occurs because SPL's linker script places .bss in a separate
> memory region (.bss_mem) from .text/.data (.spl_mem). With -fpic,
> accessing global variables uses PC-relative GOT addressing, which
> fails when the distance between code and data exceeds the 20-bit
> signed offset limit of R_RISCV_PCREL_HI20.

This sounds strange. R_RISCV_GOT_HI20 instead of R_RISCV_PCREL_HI20
should be used when addressing a variable through GOT in code. Thus I
suspect in your case, the compiler decides to address the .bss variable
PC-relatively, bypassing the GOT, possibly because it's static thus
considered non-preemptible.

Might you provide a reproducer for the problem so we could dig it
further and confirm the root cause?

Best regards,
Yao Zi

> The main U-Boot binary requires -fpic for runtime relocation support,
> but SPL runs from a fixed address and doesn't need position-independent
> code. Disable -fpic for SPL builds while keeping it enabled for the
> main U-Boot image.
> 
>    spl/u-boot-spl: all -1187 bss +4 data -2631 rodata +2440 text -1000
> 
> Signed-off-by: Michal Simek <michal.simek at amd.com>