[PATCH v3] arm: dts: socfpga: Enable 8-bit embedded device support in Agilex5 eMMC device tree
tze.yee.ng at altera.com
tze.yee.ng at altera.com
Wed May 6 05:14:44 CEST 2026
From: tzeyeeng <tzeyee.ng at altera.com>
Set SDHCI Capabilities bit18 to enable 8-bit embedded device support.
Signed-off-by: tzeyeeng <tzeyee.ng at altera.com>
---
Changes in v2:
- Remove /delete-property/ sd-uhs-sdr50 and /delete-property/
sd-uhs-sdr104 from mmc node
- Fix wording in commit message
- Update commit title
Changes in v3:
- Dropping the patch 1 as it is already applied to master.
---
arch/arm/dts/socfpga_agilex5_socdk_emmc.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/socfpga_agilex5_socdk_emmc.dts b/arch/arm/dts/socfpga_agilex5_socdk_emmc.dts
index c06781064ca..52aa92e4292 100644
--- a/arch/arm/dts/socfpga_agilex5_socdk_emmc.dts
+++ b/arch/arm/dts/socfpga_agilex5_socdk_emmc.dts
@@ -32,7 +32,7 @@
vqmmc-supply = <&emmc_io_1v8_reg>;
max-frequency = <200000000>;
sdhci-caps = <0x00000000 0x0004c800>; /* SDHCI_CAN_DO_8BIT */
- sdhci-caps-mask = <0x00000000 0x0000ff00>;
+ sdhci-caps-mask = <0x00000000 0x0004ff00>;
/* eMMC legacy mode timing configuration */
cdns,phy-dqs-timing-delay-sd-ds = <0x00780000>;
--
2.19.0
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