[PATCH v2 3/3] ddr: socfpga: Add ECC DRAM scrubbing support for Gen5/Arria10

[Yuslaimi, Alif Zakuan]

Hi Brian,

On 5/5/2026 7:08 pm, Sune Brian wrote:
> [CAUTION: This email is from outside your organization. Unless you trust the sender, do not click on links or open attachments as it may be a fraudulent email attempting to steal your information and/or compromise your computer.]
> 
> On Tue, May 5, 2026 at 2:54 PM Chee, Tien Fong
> <tien.fong.chee at altera.com> wrote:
>>
>> Hi Alif,
>>
>>
>> On 28/4/2026 11:32 am, alif.zakuan.yuslaimi at altera.com wrote:
>>> From: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi at altera.com>
>>>
>>> The SDRAM must first be rewritten by zeroes if ECC is used to initialize
>>> the ECC metadata. Make the CPU overwrite the DRAM with zeroes in such a
>>> case.
>>>
> 
> ...
> 
>> Why not remove this?
>>
> 
> Hi Alif,
> 
> Just few comments:
> 
> - If possible make it inline, extra file means extra time to compile etc.
> - To reduce the code size which I tested a bit, the text message is the easiest.
>    So possible reuse or cleanup text print if needed.
> - use "./scripts/checkpatch.pl" under the u-boot folder to clean things up.
> 
> Thanks,
> Brian

Thanks for the suggestions, I can try to play around with these options 
and see if I come across any meaningful breakthroughs for these Gen5 
variants in the future.

I'll double check the checkpatch results for the next v3 submission.

Regards,
Alif