[PATCH v2 2/3] ddr: altera: gen5: Add DRAM size checking

[Yuslaimi, Alif Zakuan]

Hi Tien Fong,

On 5/5/2026 2:17 pm, Chee, Tien Fong wrote:
> Hi Alif,
> 
> 
> On 28/4/2026 11:32 am, alif.zakuan.yuslaimi at altera.com wrote:
>> From: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi at altera.com>
>>
>> Add DRAM size checking compare between size from device tree and actual
>> hardware.
>>
>> Trigger hang if DRAM size from device tree is greater than actual 
>> hardware.
>> Display warning message if DRAM size mismatch between device tree and
>> actual hardware.
>>
>> get_ram_size() uses size from device tree. So, it has consistency with
>> other device families.
>>
>> New Kconfig is introduced to enable this implementation only on the 
>> default
>> CycloneV board as this will increase the SPL size which will exceed some
>> Gen5 devices' SPL size limit.
>>
>> Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi at altera.com>
>> ---
>>   arch/arm/mach-socfpga/Kconfig   |  9 +++++++++
>>   drivers/ddr/altera/sdram_gen5.c | 27 +++++++++++++++++++++++++++
>>   2 files changed, 36 insertions(+)
>>
>> diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/ 
>> Kconfig
>> index e2fdd6bb30f..830585a72cc 100644
>> --- a/arch/arm/mach-socfpga/Kconfig
>> +++ b/arch/arm/mach-socfpga/Kconfig
>> @@ -6,6 +6,12 @@ config ERR_PTR_OFFSET
>>   config NR_DRAM_BANKS
>>       default 1
>> +config SOCFPGA_DRAM_SIZE_CHECK
>> +    bool "Enable DRAM size checking for safety"
>> +    help
>> +     Compares device tree DRAM size with actual hardware. Hangs on
>> +     oversized claim.
>> +
>>   config SOCFPGA_SECURE_VAB_AUTH
>>       bool "Enable boot image authentication with Secure Device Manager"
>>       depends on ARCH_SOCFPGA_AGILEX || ARCH_SOCFPGA_N5X || \
>> @@ -111,6 +117,9 @@ config SOCFPGA_ARRIA10_ALWAYS_REPROGRAM
>>   config ARCH_SOCFPGA_CYCLONE5
>>       bool
>>       select ARCH_SOCFPGA_GEN5
>> +    select SOCFPGA_DRAM_SIZE_CHECK if !TARGET_SOCFPGA_TERASIC_SOCKIT \
>> +      && !TARGET_SOCFPGA_EBV_SOCRATES && \
>> +      !TARGET_SOCFPGA_SOFTING_VINING_FPGA
>>   config ARCH_SOCFPGA_GEN5
>>       bool
>> diff --git a/drivers/ddr/altera/sdram_gen5.c b/drivers/ddr/altera/ 
>> sdram_gen5.c
>> index 3c79bb11802..1c3c70ea8ae 100644
>> --- a/drivers/ddr/altera/sdram_gen5.c
>> +++ b/drivers/ddr/altera/sdram_gen5.c
>> @@ -5,6 +5,7 @@
>>   #include <dm.h>
>>   #include <errno.h>
>>   #include <div64.h>
>> +#include <hang.h>
>>   #include <init.h>
>>   #include <log.h>
>>   #include <ram.h>
>> @@ -15,6 +16,7 @@
>>   #include <asm/arch/sdram.h>
>>   #include <asm/arch/system_manager.h>
>>   #include <asm/bitops.h>
>> +#include <asm/global_data.h>
>>   #include <asm/io.h>
>>   #include <dm/device_compat.h>
>> @@ -22,6 +24,8 @@
>>   #ifdef CONFIG_XPL_BUILD
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>>   struct altera_gen5_sdram_priv {
>>       struct ram_info info;
>>   };
>> @@ -604,8 +608,31 @@ static int altera_gen5_sdram_probe(struct udevice 
>> *dev)
>>       sdram_size = sdram_calculate_size(sdr_ctrl);
>>       debug("SDRAM: %ld MiB\n", sdram_size >> 20);
>> +#if IS_ENABLED(CONFIG_SOCFPGA_DRAM_SIZE_CHECK)
>> +    /* setup the dram info within bd */
>> +    dram_init_banksize();
>> +
>> +    if (sdram_size != gd->bd->bi_dram[0].size) {
> 
> 
> Building socfpga_cyclone5_defconfig with only patch 2 applied produces a 
> binary that NULL-dereferences in the RAM probe. Not bisect-safe.
> 
> 
> Fix: Move the bdata declaration and gd->bd = &bdata assignment from 
> patch 3 spl_gen5.c into patch 2, making patch 2 self-contained.
> 
> Best regards,
> 
> Tien Fong
> 
Thanks for the suggestion. I will implement this in v3.

Alif