[PATCH] drivers: clk: n5x: update comment to describe PLL bypass

[Chen Huei Lok]

From: Jit Loon Lim <jit.loon.lim at altera.com>

The existing comments incorrectly say "Put PLLs in Reset" and
"Take PLL out of reset and power up", but the code actually toggles
the PLL bypass bit. Update the comments to accurately describe the
PLL bypass behavior.

Signed-off-by: Jit Loon Lim <jit.loon.lim at altera.com>
Signed-off-by: Chen Huei Lok <chen.huei.lok at altera.com>
---
 drivers/clk/altera/clk-mem-n5x.c | 7 +++++--
 drivers/clk/altera/clk-n5x.c     | 7 +++++--
 2 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/altera/clk-mem-n5x.c b/drivers/clk/altera/clk-mem-n5x.c
index ac59571a853..0b136b30ce6 100644
--- a/drivers/clk/altera/clk-mem-n5x.c
+++ b/drivers/clk/altera/clk-mem-n5x.c
@@ -58,7 +58,10 @@ static void clk_mem_basic_init(struct udevice *dev,
 	/* Put PLLs in bypass */
 	clk_mem_write_bypass_mempll(plat, MEMCLKMGR_BYPASS_MEMPLL_ALL);
 
-	/* Put PLLs in Reset */
+	/*
+	 * Put PLL in bypass which powers down the PLL
+	 * and bypasses it such that PLLOUT tracks REF.
+	 */
 	CM_REG_SETBITS(plat, MEMCLKMGR_MEMPLL_PLLCTRL,
 		       MEMCLKMGR_PLLCTRL_BYPASS_MASK);
 
@@ -68,7 +71,7 @@ static void clk_mem_basic_init(struct udevice *dev,
 	CM_REG_WRITEL(plat, cfg->mem_plldiv, MEMCLKMGR_MEMPLL_PLLDIV);
 	CM_REG_WRITEL(plat, cfg->mem_plloutdiv, MEMCLKMGR_MEMPLL_PLLOUTDIV);
 
-	/* Take PLL out of reset and power up */
+	/* Take PLL out of bypass */
 	CM_REG_CLRBITS(plat, MEMCLKMGR_MEMPLL_PLLCTRL,
 		       MEMCLKMGR_PLLCTRL_BYPASS_MASK);
 }
diff --git a/drivers/clk/altera/clk-n5x.c b/drivers/clk/altera/clk-n5x.c
index 185c9028a78..3495283407d 100644
--- a/drivers/clk/altera/clk-n5x.c
+++ b/drivers/clk/altera/clk-n5x.c
@@ -63,7 +63,10 @@ static void clk_basic_init(struct udevice *dev,
 	clk_write_bypass_mainpll(plat, CLKMGR_BYPASS_MAINPLL_ALL);
 	clk_write_bypass_perpll(plat, CLKMGR_BYPASS_PERPLL_ALL);
 
-	/* Put both PLLs in Reset */
+	/*
+	 * Put both PLLs in bypass which power down the PLLs
+	 * and bypasses it such that PLLOUT tracks REF.
+	 */
 	CM_REG_SETBITS(plat, CLKMGR_MAINPLL_PLLCTRL,
 		       CLKMGR_PLLCTRL_BYPASS_MASK);
 	CM_REG_SETBITS(plat, CLKMGR_PERPLL_PLLCTRL,
@@ -84,7 +87,7 @@ static void clk_basic_init(struct udevice *dev,
 	CM_REG_WRITEL(plat, cfg->per_pll_emacctl, CLKMGR_PERPLL_EMACCTL);
 	CM_REG_WRITEL(plat, cfg->per_pll_gpiodiv, CLKMGR_PERPLL_GPIODIV);
 
-	/* Take both PLL out of reset and power up */
+	/* Take both PLLs out of bypass */
 	CM_REG_CLRBITS(plat, CLKMGR_MAINPLL_PLLCTRL,
 		       CLKMGR_PLLCTRL_BYPASS_MASK);
 	CM_REG_CLRBITS(plat, CLKMGR_PERPLL_PLLCTRL,
-- 
2.43.7