[PATCH v4 8/9] arm: dts: mt8189: Add ethernet support for Genio 520/720 boards
Macpaul Lin (林智斌)
Macpaul.Lin at mediatek.com
Mon May 11 12:34:00 CEST 2026
On Wed, 2026-04-29 at 15:59 +0200, Julien Stephan wrote:
> Add Ethernet support for MediaTek MT8189-based Genio 520 and Genio
> 720
> development boards.
>
> The ethernet interface is disabled by default in the SoC dtsi and
> enabled in the board-specific configuration with proper PHY settings.
>
> The ethernet related nodes are not part of current dt submission on
> the
> kernel [1] and come from downstream u-boot. When switching to
> OF_UPSTREAM we should add them back.
>
> [1]:
> https://lore.kernel.org/all/20251203-add-mediatek-genio-520-720-evk-v1-3-df794b2a30ae@collabora.com/
>
> Signed-off-by: Julien Stephan <jstephan at baylibre.com>
> ---
> arch/arm/dts/mt8189.dtsi | 77
> ++++++++++++++++++++++++++++++++
> arch/arm/dts/mt8371-genio-common.dtsi | 83
> +++++++++++++++++++++++++++++++++++
> 2 files changed, 160 insertions(+)
>
> diff --git a/arch/arm/dts/mt8189.dtsi b/arch/arm/dts/mt8189.dtsi
> index e550745ac5d..d4ee268a298 100644
> --- a/arch/arm/dts/mt8189.dtsi
> +++ b/arch/arm/dts/mt8189.dtsi
> @@ -364,6 +364,83 @@
> #reset-cells = <1>;
> };
>
> + eth: ethernet at 1101a000 {
> + compatible = "mediatek,mt8189-gmac",
> "snps,dwmac-5.10a";
> + reg = <0 0x1101a000 0 0x4000>;
> + interrupts = <GIC_SPI 475
> IRQ_TYPE_LEVEL_HIGH 0>;
> + interrupt-names = "macirq";
> + clock-names = "mac_main",
> + "ptp_ref";
> + clocks = <&topckgen_clk
> CLK_TOP_ETH_250M_SEL>,
> + <&topckgen_clk
> CLK_TOP_ETH_62P4M_PTP_SEL>;
> + assigned-clocks = <&topckgen_clk
> CLK_TOP_ETH_250M_SEL>,
> + <&topckgen_clk
> CLK_TOP_ETH_62P4M_PTP_SEL>,
> + <&topckgen_clk
> CLK_TOP_ETH_50M_RMII_SEL>;
> + assigned-clock-parents = <&topckgen_clk
> CLK_TOP_ETHPLL_D2>,
> + <&topckgen_clk
> CLK_TOP_ETHPLL_D8>,
> + <&topckgen_clk
> CLK_TOP_ETHPLL_D10>;
> + mediatek,pericfg = <&pericfg_ao_clk>;
> + snps,axi-config = <&stmmac_axi_setup>;
> + snps,mtl-rx-config = <&mtl_rx_setup>;
> + snps,mtl-tx-config = <&mtl_tx_setup>;
> + snps,txpbl = <16>;
> + snps,rxpbl = <16>;
> + clk-csr = <4>;
> + status = "disabled";
> +
> + stmmac_axi_setup: stmmac-axi-config {
> + snps,wr-osr-lmt = <0x7>;
> + snps,rd-osr-lmt = <0x7>;
> + snps,blen = <0 0 0 0 16 8 4>;
> + };
> +
> + mtl_rx_setup: rx-queues-config {
> + snps,rx-queues-to-use = <4>;
> + snps,rx-sched-sp;
> + queue0 {
> + snps,dcb-algorithm;
> + snps,map-to-dma-channel =
> <0x0>;
> + };
> + queue1 {
> + snps,dcb-algorithm;
> + snps,map-to-dma-channel =
> <0x0>;
> + };
> + queue2 {
> + snps,dcb-algorithm;
> + snps,map-to-dma-channel =
> <0x0>;
> + };
> + queue3 {
> + snps,dcb-algorithm;
> + snps,map-to-dma-channel =
> <0x0>;
> + };
> + };
> +
> + mtl_tx_setup: tx-queues-config {
> + snps,tx-queues-to-use = <4>;
> + snps,tx-sched-wrr;
> + queue0 {
> + snps,weight = <0x10>;
> + snps,dcb-algorithm;
> + snps,priority = <0x0>;
> + };
> + queue1 {
> + snps,weight = <0x11>;
> + snps,dcb-algorithm;
> + snps,priority = <0x1>;
> + };
> + queue2 {
> + snps,weight = <0x12>;
> + snps,dcb-algorithm;
> + snps,priority = <0x2>;
> + };
> + queue3 {
> + snps,weight = <0x13>;
> + snps,dcb-algorithm;
> + snps,priority = <0x3>;
> + };
> + };
> + };
> +
> topckgen_clk: clock-controller at 10000000 {
> compatible = "mediatek,mt8189-topckgen",
> "syscon";
> reg = <0 0x10000000 0 0x1000>;
> diff --git a/arch/arm/dts/mt8371-genio-common.dtsi
> b/arch/arm/dts/mt8371-genio-common.dtsi
> index 046e9d57752..1376a4c378c 100644
> --- a/arch/arm/dts/mt8371-genio-common.dtsi
> +++ b/arch/arm/dts/mt8371-genio-common.dtsi
> @@ -281,6 +281,68 @@
> bias-pull-up;
> };
> };
> +
> + eth_default_pins: eth-default-pins {
> + txd-pins {
> + pinmux = <PINMUX_GPIO119__FUNC_GBE_TXD3>,
> + <PINMUX_GPIO120__FUNC_GBE_TXD2>,
> + <PINMUX_GPIO121__FUNC_GBE_TXD1>,
> + <PINMUX_GPIO122__FUNC_GBE_TXD0>;
> + drive-strength = <MTK_DRIVE_8mA>;
> + };
> + cc-pins {
> + pinmux = <PINMUX_GPIO127__FUNC_GBE_TXC>,
> + <PINMUX_GPIO130__FUNC_GBE_TXEN>,
> + <PINMUX_GPIO129__FUNC_GBE_RXDV>,
> + <PINMUX_GPIO128__FUNC_GBE_RXC>;
> + drive-strength = <MTK_DRIVE_8mA>;
> + };
> + rxd-pins {
> + pinmux = <PINMUX_GPIO123__FUNC_GBE_RXD3>,
> + <PINMUX_GPIO124__FUNC_GBE_RXD2>,
> + <PINMUX_GPIO125__FUNC_GBE_RXD1>,
> + <PINMUX_GPIO126__FUNC_GBE_RXD0>;
> + drive-strength = <MTK_DRIVE_8mA>;
> + };
> + mdio-pins {
> + pinmux = <PINMUX_GPIO131__FUNC_GBE_MDC>,
> + <PINMUX_GPIO132__FUNC_GBE_MDIO>;
> + drive-strength = <MTK_DRIVE_8mA>;
> + input-enable;
> + };
> + power-pins {
> + pinmux = <PINMUX_GPIO133__FUNC_GPIO133>,
> + <PINMUX_GPIO134__FUNC_GPIO134>;
> + output-high;
> + };
> + };
> +
> + eth_sleep_pins: eth-sleep-pins {
> + txd-pins {
> + pinmux = <PINMUX_GPIO119__FUNC_GPIO119>,
> + <PINMUX_GPIO120__FUNC_GPIO120>,
> + <PINMUX_GPIO121__FUNC_GPIO121>,
> + <PINMUX_GPIO122__FUNC_GPIO122>;
> + };
> + cc-pins {
> + pinmux = <PINMUX_GPIO127__FUNC_GPIO127>,
> + <PINMUX_GPIO130__FUNC_GPIO130>,
> + <PINMUX_GPIO129__FUNC_GPIO129>,
> + <PINMUX_GPIO128__FUNC_GPIO128>;
> + };
> + rxd-pins {
> + pinmux = <PINMUX_GPIO123__FUNC_GPIO123>,
> + <PINMUX_GPIO124__FUNC_GPIO124>,
> + <PINMUX_GPIO125__FUNC_GPIO125>,
> + <PINMUX_GPIO126__FUNC_GPIO126>;
> + };
> + mdio-pins {
> + pinmux = <PINMUX_GPIO131__FUNC_GPIO131>,
> + <PINMUX_GPIO132__FUNC_GPIO132>;
> + input-disable;
> + bias-disable;
> + };
> + };
> };
>
> &pmic {
> @@ -311,3 +373,24 @@
> vbus-supply = <&usb_p4_vbus>;
> status = "okay";
> };
> +
> +ð {
> + /*
> + * TX clock is provided by MAC
> + */
> + phy-mode = "rgmii-rxid";
> + phy-handle = <&phy>;
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <ð_default_pins>;
> + pinctrl-1 = <ð_sleep_pins>;
> + status = "okay";
> + mdio {
> + compatible = "snps,dwmac-mdio";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + phy: phy at 0 {
> + compatible = "ethernet-phy-idc0ff.0421";
> + reg = <0>;
> + };
> + };
> +};
>
Reviewed-by: Macpaul Lin <macpaul.lin at mediatek.com>
Thanks
Macpaul Lin
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