[PATCH v2 0/3] SoCFPGA: Update DDR Support for Gen5/Arria10 in U-Boot

[Yuslaimi, Alif Zakuan]

Hi Brian,

On 7/5/2026 7:04 pm, Sune Brian wrote:
> [CAUTION: This email is from outside your organization. Unless you trust the sender, do not click on links or open attachments as it may be a fraudulent email attempting to steal your information and/or compromise your computer.]
> 
> On Thu, Apr 23, 2026 at 4:06 PM <alif.zakuan.yuslaimi at altera.com> wrote:
>>
>> From: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi at altera.com>
>>
>> This patch set updates the boot support for the Altera SoCFPGA Gen5/Arria10 platform in U-Boot. The changes include:
>>          1. Update MMU/dcache setup across Gen5/Arria10 using common driver
>>          2. Add ECC scrubbing support for Gen5/Arria10
>>          3. Add DRAM size checking for Gen5/Arria10
>>
>> This patch set has been tested on CycloneV devkit with SDMMC boot and RAM boot (TFTP & ARM DS debugger).
>> Tested on Arria10 devkit with RAM boot as well
>>
>> v1->v2:
>> --------
>> - ECC scrubbing, Gen5 DRAM size checking, and shared dram_bank_mmu_setup() is set as optional via Kconfig and
>>    defaulted on only for the reference Arria10/CycloneV boards to avoid SPL overflows on size-limited Gen5
>>    defconfigs.
> 
> Well, I don't know I am only a contributor after all:
> 1) But do some one or some ones clearly mentioned [1]
> 2) Per-version change history must be placed below the '---' separator.
>      The required format is 'Changes in vN:'. Custom formats are not
>      acceptable.
> 
> So v1->v2 is considered as a valid format and not a custom format.
> Hum, interesting.
> 
> What a wonderful world =]
> 
> Appreciated all the "reviewers" HAHA :D
> 
> Brian
> 
> [1] https://docs.u-boot.org/en/latest/develop/sending_patches.html#sending-updated-patch-versions
> 

Thanks for pointing this out, I will correct the format for v3 submission.

Best regards,
Alif

>>
>> History:
>> --------
>> [v1]: https://patchwork.ozlabs.org/project/uboot/cover/20251216084623.19589-1-alif.zakuan.yuslaimi@altera.com/
>>
>> Alif Zakuan Yuslaimi (3):
>>    arm: socfpga: Consolidate dram_bank_mmu_setup()
>>    ddr: altera: gen5: Add DRAM size checking
>>    ddr: socfpga: Add ECC DRAM scrubbing support for Gen5/Arria10
>>
>>   arch/arm/mach-socfpga/Kconfig        | 21 +++++++
>>   arch/arm/mach-socfpga/misc.c         | 31 ++++++++++
>>   arch/arm/mach-socfpga/misc_arria10.c | 26 ---------
>>   arch/arm/mach-socfpga/spl_a10.c      |  4 ++
>>   arch/arm/mach-socfpga/spl_gen5.c     | 17 ++++++
>>   drivers/ddr/altera/Makefile          |  4 +-
>>   drivers/ddr/altera/sdram_arria10.c   | 34 +++++------
>>   drivers/ddr/altera/sdram_gen5.c      | 64 ++++++++++++++++++++-
>>   drivers/ddr/altera/sdram_soc32.c     | 85 ++++++++++++++++++++++++++++
>>   drivers/ddr/altera/sdram_soc32.h     | 15 +++++
>>   10 files changed, 252 insertions(+), 49 deletions(-)
>>   create mode 100644 drivers/ddr/altera/sdram_soc32.c
>>   create mode 100644 drivers/ddr/altera/sdram_soc32.h
>>
>> --
>> 2.43.7
>>