[PATCH 7/7] doc: board: phytec: Document DDR size override Kconfigs

[Wadim Egorov]

The phyCORE-AM62x and phyCORE-AM64x R5 SPL detects the populated DDR
size from the SoM EEPROM and falls back to 2 GB if detection fails. For
boards without a populated EEPROM or if no detection needed, the detection
can be bypassed via CONFIG_PHYCORE_AM6{2,4}X_RAM_SIZE_FIX and one of
the CONFIG_PHYCORE_AM6{2,4}X_RAM_SIZE_<size> choices.

Add a "DDR RAM Size" section to both board docs describing this
behaviour and listing the available size options (1/2/4 GB for AM62x,
1/2 GB for AM64x).

Signed-off-by: Wadim Egorov <w.egorov at phytec.de>
---
 doc/board/phytec/phycore-am62x.rst | 19 +++++++++++++++++++
 doc/board/phytec/phycore-am64x.rst | 18 ++++++++++++++++++
 2 files changed, 37 insertions(+)

diff --git a/doc/board/phytec/phycore-am62x.rst b/doc/board/phytec/phycore-am62x.rst
index f5a0d51240a..5349ba429d4 100644
--- a/doc/board/phytec/phycore-am62x.rst
+++ b/doc/board/phytec/phycore-am62x.rst
@@ -177,6 +177,25 @@ Boot switches should be changed with power off.
      - 11001010
      - 00100000
 
+DDR RAM Size
+------------
+
+By default, the R5 SPL detects the populated DDR size by reading the SoM
+EEPROM and configures the DDR controller and the U-Boot device-tree memory
+node accordingly. The phyCORE-AM62x is available with 1 GB, 2 GB, or 4 GB of
+DDR. If the EEPROM cannot be read or is invalid, the SPL falls back to a
+2 GB configuration.
+
+EEPROM-based detection can be bypassed by enabling
+`CONFIG_PHYCORE_AM62X_RAM_SIZE_FIX` in the R5 defconfig and selecting one of:
+
+* `CONFIG_PHYCORE_AM62X_RAM_SIZE_1GB`
+* `CONFIG_PHYCORE_AM62X_RAM_SIZE_2GB`
+* `CONFIG_PHYCORE_AM62X_RAM_SIZE_4GB`
+
+This is mainly useful if no detection is needed or for boards without a
+populated SoM EEPROM.
+
 .. include:: k3-common.rst
 
 Further Information
diff --git a/doc/board/phytec/phycore-am64x.rst b/doc/board/phytec/phycore-am64x.rst
index c6677f6a440..20887d443a9 100644
--- a/doc/board/phytec/phycore-am64x.rst
+++ b/doc/board/phytec/phycore-am64x.rst
@@ -175,6 +175,24 @@ Boot switches should be changed with power off.
      - 11011100
      - 00000000
 
+DDR RAM Size
+------------
+
+By default, the R5 SPL detects the populated DDR size by reading the SoM
+EEPROM and configures the DDR controller and the U-Boot device-tree memory
+node accordingly. The phyCORE-AM64x is available with 1 GB or 2 GB of DDR.
+If the EEPROM cannot be read or is invalid, the SPL falls back to a 2 GB
+configuration.
+
+EEPROM-based detection can be bypassed by enabling
+`CONFIG_PHYCORE_AM64X_RAM_SIZE_FIX` in the R5 defconfig and selecting one of:
+
+* `CONFIG_PHYCORE_AM64X_RAM_SIZE_1GB`
+* `CONFIG_PHYCORE_AM64X_RAM_SIZE_2GB`
+
+This is mainly useful if no detection is needed or for boards without a
+populated SoM EEPROM.
+
 .. include:: k3-common.rst
 
 Further Information
-- 
2.48.1